J. Barbolla

Universidad de Valladolid, Valladolid, Castille and León, Spain

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Publications (121)

  • Lourdes Pelaz · J. Vicente · M. Jaraiz · [...] · J. Barbolla
    Article · Jan 2011 · MRS Online Proceeding Library Archive
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    Full-text Article · Jan 2011 · MRS Online Proceeding Library Archive
  • S. Dueñas · H. Castán · J. Barbolla · [...] · P.A. Sullivan
    [Show abstract] [Hide abstract] ABSTRACT: In this work we report on tantalum oxide fabricated by anodic oxidation of tantalum nitride and tantalum suicide to be used as the dielectric of Metal-Insulator-Metal (M1M) capacitors. These films exhibit greatly improved leakage currents, breakdown voltage and very low defect density, thus allowing the fabrication of large area capacitors. Several counter and bottom electrodes have been used and compared. The effects of the different processing conditions (top-electrode metals, annealing conditions, bottom electrode stoichiometry and precursor) on the capacitor performances are extensively discussed throughout this work. The electrical behavior of the resulting high-density MIM capacitors has been extensively characterized. Finally, we propose a set of selection guides to select the more appropriate process parameter values and electrode materials for a given application of these capacitors.
    Article · Jan 2011 · MRS Online Proceeding Library Archive
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    H. Castán · S. Dueñas · J. Barbolla · [...] · G. González-Díaz
    [Show abstract] [Hide abstract] ABSTRACT: A study of metal-insulator-semiconductor (MIS) structures based on SiN x, SiO2/SiNx and SiOxNy films deposited on silicon by electron cyclotron resonance plasma-enhanced chemical vapour deposition (ECR-PECVD) is presented. Interface trap densities measured by deep level transient spectroscopy (DLTS) are higher for silicon oxynitride-based MIS capacitors than for silicon nitride and silicon oxide-silicon nitride-based ones, However, conductance transient analysis demonstrated that Al/SiNx/Si devices exhibit the highest disordered-induced gap states (DIGS) density, whereas the lowest one corresponds to Al/SiNx/SiO2/Si, and silicon oynitridebased MIS capacitors show an intermediate behaviour. In addition, thermal treatments applied to Al/SiOxNy/Si samples reduce DIGS densities to values even lower than those corresponding to Al/SiNx/SiO 2/Si devices.
    Full-text Article · Jan 2011 · MRS Online Proceeding Library Archive
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    H. Castán · S. Dueñas · J. Barbolla · [...] · G. González-Díaz
    [Show abstract] [Hide abstract] ABSTRACT: As it has been shown elsewhere, conductance transient measurements provide quantitative information about the disordered induced gap states (DIGS) in metal-insulator-semiconductor (MIS) structures. In this work we report for the first time the DIGS spatial and energetical distribution obtained by recording conductance transients at several temperatures (ranging from 77 to 300 K) and several frequencies (ranging from 100 Hz to 200 KHz). These measurements allow us to obtain three-dimensional defect maps of Al/SiNx:H/InP structures browsing ranges of 0.5 eV in energy and 40 Å in depth. Our results show that this technique is a very useful tool for the electrical characterization of MIS structures and reveals itself as very valuable in the III-V semiconductor-field-effect transistor scenario.
    Full-text Article · Jan 2011 · MRS Online Proceeding Library Archive
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    J.E. Rubio · M. Jaraiz · I. Martin-Bragado · [...] · J. Barbolla
    [Show abstract] [Hide abstract] ABSTRACT: Continuum downscaling of MOSFET devices requires of ultra-shallow junction formation. Performance of the source and drain from B and As low energy implant and subsequent annealing is seriously affected by the presence of the Si–SiO2 interface. Dopant loss due to segregation and dopant pileup at the interface during the transient enhanced diffusion (TED) are crucial phenomena for current and future CMOS devices. In this work we have implemented the Oh-Ward model [Y.-S. Oh, D.E. Ward, Tech. Dig. Int. Electron Devices Meet. 1998 (1998) 509] for the dopant behaviour at the interfaces integrated in an atomistic kinetic Monte Carlo simulator. Dopant traps at the interface can capture from or emit to either side of the interface. Furthermore, segregation of dopants and saturation of the interface by the presence of other species are also included. As a test of the model, low energy implants through a screen oxide have been simulated. When annealing these very shallow implants, a pileup at the interface is observed. The mechanisms involved in this process, as well as its dependence on the implant dose and energy are discussed.
    Full-text Article · Dec 2005 · Materials Science and Engineering B
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    P Castrillo · I Martin-Bragado · R Pinacho · [...] · J Barbolla
    [Show abstract] [Hide abstract] ABSTRACT: Under certain conditions, particularly for high-dose implants, {3 1 1} rod-like defects can evolve into dislocation loops (DLs). In this work, we have developed a model for the transformation of {3 1 1}-defects into DLs, with a transformation rate that is controlled by a size-dependent energy barrier. The model has been included and calibrated in an atomistic kinetic Monte Carlo simulator. This simulator includes a description of the size distribution of {3 1 1}-defects (required for a size-based model) and of the amorphization and recrystallization (needed to provide reliable information on the number of interstitials in the end-of-range region). Extended defects are implemented according to realistic geometries, giving a direct assessment of the correct capture volume for diffusing defects. The model correctly predicts the formation of DLs during the annealing that follows ion implants, both for amorphizing and non-amorphizing conditions, and provides a realistic description of damage morphology. The possible role of stress on DL formation is also discussed.
    Full-text Article · Dec 2005 · Materials Science and Engineering B
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    [Show abstract] [Hide abstract] ABSTRACT: Atomistic process simulation is expected to play an important role for the development of next generations of integrated circuits. This work describes an approach for modeling electric charge effects in a three-dimensional atomistic kinetic Monte Carlo process simulator. The proposed model has been applied to the diffusion of electrically active boron and arsenic atoms in silicon. Several key aspects of the underlying physical mechanisms are discussed: (i) the use of the local Debye length to smooth out the atomistic point-charge distribution, (ii) algorithms to correctly update the charge state in a physically accurate and computationally efficient way, and (iii) an efficient implementation of the drift of charged particles in an electric field. High-concentration effects such as band-gap narrowing and degenerate statistics are also taken into account. The efficiency, accuracy, and relevance of the model are discussed.
    Full-text Article · Oct 2005 · Journal of Applied Physics
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    [Show abstract] [Hide abstract] ABSTRACT: We introduce a model for damage accumulation up to amorphization, based on the ion-implant damage structures commonly known as amorphous pockets. The model is able to reproduce the silicon amorphous-crystalline transition temperature for C, Si, and Ge ion implants. Its use as an analysis tool reveals an unexpected bimodal distribution of the defect population around a characteristic size, which is larger for heavier ions. The defect population is split in both size and composition, with small, pure interstitial and vacancy clusters below the characteristic size, and amorphous pockets with a balanced mixture of interstitials and vacancies beyond that size.
    Full-text Article · Sep 2005 · Journal of Applied Physics
  • J. Arias · L. Quintanilla · D. Bisbal · [...] · J. Barbolla
    [Show abstract] [Hide abstract] ABSTRACT: In this work, an approach for the simulation of the effect of noise sources in the performance of continuous-time DeltaSigma modulators is presented. Electrical noise including thermal noise, /f noise and clock jitter are included in a simulation program and their impact on the system performance is analyzed.
    Article · Aug 2005
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    I. Martin-Bragado · P. Castrillo · M. Jaraiz · [...] · J. Barbolla
    [Show abstract] [Hide abstract] ABSTRACT: An accurate physically based Fermi-level modeling approach, amenable to be implemented in an atomistic process simulator, is reported. The atomistic kinetic Monte Carlo method is used for point and extended defects, in conjunction with a quasiatomistic, continuum approach treatment for carrier densities. The model implements charge reactions and electric bias according to the local Fermi level, pairing and break-up reactions between particles, clustering-related dopant deactivation, and Fermi-level-dependent solubility. We derive expressions that can be used as a bridge between the continuum and the atomistic frameworks. We present the implementation of two common dopants, boron and arsenic, using parameters that are in agreement with both ab initio calculations and experimental results.
    Full-text Article · Jul 2005 · Physical Review B
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    R. Pinacho · M. Jaraiz · P. Castrillo · [...] · J. Barbolla
    [Show abstract] [Hide abstract] ABSTRACT: A comprehensive atomistic model for arsenic in silicon which includes charge effects and is consistent with first-principles calculations for arsenic-vacancy cluster energies has been developed. Emphasis has been put in reproducing the electrical deactivation and the annealed profiles in preamorphized silicon. The simulations performed with an atomistic kinetic Monte Carlo simulator suggest a predominant role of the mobile interstitial arsenic in deactivation experiments and provide a good understanding of the arsenic behavior in preamorphized silicon during annealing.
    Full-text Article · Jul 2005 · Applied Physics Letters
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    J. San Pablo · D. Bisbal · L. Quintanilla · [...] · J. Barbolla
    [Show abstract] [Hide abstract] ABSTRACT: A comparison is presented for three different feedback signal shapes on a current mode continuous-time second order sigma-delta modulator, although, it can be extended to systems of any order. The three shapes are: rectangular, exponential, and a new mixed waveform whose pulse starts being rectangular and after a fraction of the clock period changes to decaying ramp. Simulation results at system level, using a software model, are presented. Results show that using early return to zero feedback signal shapes (exponential, mixed) the modulator performance degradation due to pulse width variation is reduced with respect to rectangular signal shapes. In addition to that, the new mixed shaped do not present the high signal peak that the exponential does. This is important from the point of view of integrator input stage because it allows power saving as well as critical input noise reduction.
    Full-text Article · Jun 2005 · Proceedings of SPIE - The International Society for Optical Engineering
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    J. Arias · P. Kiss · V. Prodanov · [...] · J. Barbolla
    [Show abstract] [Hide abstract] ABSTRACT: In this work a dual-mode complex multibit continuous-time DS modulator for a standard 0.25µm CMOS technol- ogy is presented. This modulator is intended for the analog-to-digital conversion in multi-mode wireless-LAN receivers (802.11a/b/g) which require wide bandwidth and moderate resolution. Then, a low oversampling ratio of 16 along with a clock frequency of 320 MHz provides a signal bandwidth of 20 MHz for a 9-bit resolution with a second-order modulator. The modulator can be congured for two different modes of operation depending on the type of radio receiver chosen: "zero- IF" (ZIF) and "low-IF" (LIF). The former mode is better suited for 802.11b, while LIF mode is more adequate for 802.11a/g applications. The loop lter is based on transconductors and MOS-capacitors allowing for low power consumption and small chip area. The modulator also includes two 3-bit quantizers, both with their corresponding DWA scrambler. The supply volt- age is 2.5V and the measured power consumption is 32 mW. Experimental results using both sine-wave and OFDM signals are presented. The obtained SNR and SNDR are 55dB and 53.5dB, respectively. A high image rejection of 47dB is achieved owing to proper layout techniques. When using OFDM signals, a minimum error vector magnitude of 1.3% is obtained. Finally, the active chip area is 0:44mm2.
    Full-text Article · Jun 2005 · Proceedings of SPIE - The International Society for Optical Engineering
  • J Arias · P Kiss · V Boccuzzi · [...] · J Barbolla
    [Show abstract] [Hide abstract] ABSTRACT: This paper presents a digital correction technique for wide-band multibit error-feedback (EF) digital-to-analog converters (DACs). The integral nonlinearity (INL) error of the multibit DAC is estimated (on line or off line) by a calibration analog-to-digital converter (CADC) and stored in a random-access memory table. The INL values are then used to compensate for the multibit DAC's distortion by a simple digital addition. The accuracy requirements for the error estimates are derived. These requirements can be significantly relaxed when the correction is combined with data-weighted averaging (DWA). Simulation and discrete-component measurement results are presented for a fourth-order 5-bit EF DAC. The results show a 14-bit DAC operating at an oversampling ratio of 8, which is suitable for digital subscriber line applications. The correction uses simple digital circuitry and a 3-bit CADC enhanced by DWA.
    Article · Jun 2005 · IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications
  • [Show abstract] [Hide abstract] ABSTRACT: An electrical characterization comparative analysis between Al/HfO2/n-Si and Al/Hf-Si-O/n-Si samples has been carried out. Hafnium-based dielectric films have been grown by means of atomic layer deposition (ALD). Interface quality have been determined by using capacitance–voltage (C–V), deep level transient spectroscopy (DLTS) and conductance transient (G-t) techniques. Our results show that silicate films exhibit less flat-band voltage shift and hysteresis effect, and so lower disordered induced gap states (DIGS) density than oxide films, but interfacial state density is greater in Hf–Si–O than in HfO2. Moreover, a post-deposition annealing in vacuum under N2 flow for 1 min, at temperatures between 600 and 730 °C diminishes interfacial state density of Hf–Si–O films to values measured in HfO2 films, without degrade the interface quality in terms of DIGS.
    Article · May 2005 · Microelectronics Reliability
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    [Show abstract] [Hide abstract] ABSTRACT: We investigate the influence of the used cleaning method and rapid thermal annealing (RTA) conditions on the electrical characteristics of MIS devices based on SiNy:H/SiOx dielectric stack structures fabricated by electron-cyclotron-resonance plasma assisted chemical vapour deposition (ECR-CVD). We use capacitance–voltage (C–V) technique to study charge trapped in the insulator, Deep Level Transient Spectroscopy (DLTS) to study the trap distributions at the interface, and conductance transient (G–t) technique to determine the energy and geometrical profiles of electrically active defects at the insulator bulk as these defects follow the disorder-induced gap state (DIGS) model.
    Full-text Article · May 2005 · Microelectronics Reliability
  • [Show abstract] [Hide abstract] ABSTRACT: An electrical characterization of Al/Hf-Si-O/n-Si samples has been carried out. Hafnium-rich silicate films have been grown by means of atomic layer deposition (ALD). Capacitance-voltage (C-V), deep level transient spectroscopy (DLTS) and conductance transient (G-t) techniques have been used. Although as-deposited samples exhibit high interfacial state and disordered induced gap state densities, a post-metallization thermal annealing in vacuum under N<sub>2</sub> flow for 1 min. at temperatures between 600 and 730 °C clearly improves the interface quality. Moreover, both as-deposited and annealed samples show low flat-band voltage shift and hysteresis effect. These results confirm Hf silicate as a suitable candidate to replace SiO<sub>2</sub> as gate dielectric in future CMOS technologies.
    Conference Paper · Mar 2005
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    [Show abstract] [Hide abstract] ABSTRACT: A comparison between interface quality of several temperatures thermal annealed HPRS TiO<sub>2</sub> films and 750 °C annealed ALD TiO<sub>2</sub> films has been established. Our attention has been focused on the interfacial state and disordered induced gap state densities. From our results, HPRS films submitted to in situ 900 °C thermal annealing in oxygen atmosphere exhibit the best characteristics, with D<sub>it</sub> density being the lowest value measured in this work (5.6 × 10<sup>11</sup> cm<sup>-2</sup> eV<sup>-1</sup>), and undetectable conductance transients within our experimental limits.
    Full-text Conference Paper · Mar 2005
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    [Show abstract] [Hide abstract] ABSTRACT: We analyze the effects of junction formation by low-temperature solid phase epitaxial regrowth in NMOS transistors. Atomistic simulations indicate that the high concentration of Si interstitials associated with the end of range (EOR) defects favors the local formation of boron clusters just beyond the amorphous/crystalline interface, in agreement to sheet resistance measurements. Thus, EOR defects locally deactivate B in the NMOS pockets. These boron clusters start dissolution, and thus B reactivates, when the high Si interstitial supersaturation produced by the EOR defects decays close to the equilibrium value. This occurs when EOR defects dissolve or evolve to very stable configurations, such us dislocation loops.
    Full-text Conference Paper · Mar 2005

Publication Stats

1k Citations

Institutions

  • 1986-2011
    • Universidad de Valladolid
      • • Department of Electricity and Electronics
      • • Facultad de Ciencias
      Valladolid, Castille and León, Spain
  • 2005
    • Complutense University of Madrid
      • Department of Applied Physics III (Electricity and Electronic)
      Madrid, Madrid, Spain
  • 2000
    • University of Barcelona
      • Department of Electronics
      Barcino, Catalonia, Spain
  • 1992
    • Autonomous University of Barcelona
      Cerdanyola del Vallès, Catalonia, Spain