F.J. Meyer

Northeastern University, Boston, Massachusetts, United States

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Publications (33)8.12 Total impact

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    Z.D. Patitz · N. Park · Minsu Choi · F.J. Meyer
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    ABSTRACT: This paper presents reliable QCA cell structures for designing single clock-controlled majority gates with a tolerance to radius of effect-induced faults, for use as a basic building component for carry look-ahead adder. Realizable quantum computing is still well in the future due to the complexity of the quantum mechanics that govern them. In this regard, QCA-based system design is a challenging task since each cell's state must interact with all the cells that are in its energy-effective range in its clocking zone, referred to as its radius of effect. This paper proposes a design approach for majority gates to overcome the constraints imposed by the radius of effect of each cell with respect to clock controls. Radius of effect induces faults that lead to constraints on the clocking scheme of majority gates. We show majority gate structures that operate with multiple radius of effect-induced faults under a single clock control. The proposed design approach to a single clock controlled majority gate ultimately facilitate more efficient and flexible clocking schemes for complex QCA designs.
    Full-text · Conference Paper · Nov 2005
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    M. Ottavi · L. Schiano · X. Wang · Y.B. Kim · F.J. Meyer · F. Lombardi
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    ABSTRACT: With the increasing needs for memory testing and repair, yield evaluation is an essential decision-making factor to define redundancy allocation and testing strategies. In particular, yield evaluation can resolve the many issues revolving around cost-effective BIST solutions and purely ATE based techniques to guarantee higher test transparency. In this document, two different yield calculation methodologies for SRAM arrays are presented. General yield calculation formulas for VLSI chips are initially presented. The regular repetitive structure of a RAM array is considered because it shows major yield improvements with the introduction of redundancy. Two repair yield evaluation formulas for a 1D redundant array are introduced and compared; the first one is based on Markov modeling, the second one is based on an approximation.
    Preview · Conference Paper · Jun 2004
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    ABSTRACT: The objective of this paper is to provide a framework by which jitter phenomena, which are encountered at the output signals of a head board in an automatic test equipment (ATE), can be studied. In this paper, the jitter refers to the one caused by radiated electromagnetic interference (EMI) noise, which is present in the head of all ATE due to DC-DC converter activity. An initial analysis of the areas of the head board most sensitive to EMI noise has been made. It identifies a sensitive part in the loop filler of a phase locked loop which is used to obtain a high frequency clock for the timing generator. Different H-fields are then applied externally at the loop filter to verify the behavior of the output signal of the head board in terms of RMS jitter. As for RMS jitter measurements, a frequency domain methodology has been employed. A trend for RMS jitter variation with respect to radiated EMI magnitude as well as frequency has been obtained. Also the orientation of the external H-field source with respect to the target board and its effects on the measured RMS jitter has been investigated. For measuring the RMS value, a proper circuitry has been designed on a daughter board to circumvent ground noise and connectivity problems arising from the head environment.
    Preview · Conference Paper · Jun 2004
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    Y.J. Lee · T. Kane · J.-J. Lim · L. Schiano · YB Kim · F.J. Meyer · F. Lombardi · S. Max
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    ABSTRACT: This paper deals with the generation, measurement and modeling of the jitter encountered in the signals of a testhead board for automatic test equipment (ATE). A novel model is proposed for the jitter; this model takes into account the radiated electromagnetic interference (EMI) noise in the head of an ATE. The RMS value of the jitter is measured at the output signal of the testhead board to validate the proposed model. For measuring the RMS value, a novel circuitry has been designed on a daughter board to circumvent ground noise and connectivity problems arising from the head environment. An H-field is applied externally at the loop filter of a phase-locked loop (PLL), thus permitting the measurement of the RMS jitter to verify the transfer function between radiated EMI and jitter variation. The error between measured and predicted jitters is within a 15% level at both 200 kHz and 500 kHz.
    Preview · Article · Jan 2004 · IEEE Transactions on Instrumentation and Measurement
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    ABSTRACT: Recent research on modeling timing jitter has raised a requirement for a predictable, high magnitude, uniform, and wide bandwidth H-field. In this paper, a novel H-field generator design methodology is proposed. It consists of a single layer air core solenoid and a digital power switch driver that takes advantage of low power, wide bandwidth, and big current-driven capability. With input overdrive voltage, the digital switch can drive rail-to-rail voltage with output current up to 16A and power bandwidth more than 3 MHz. This paper demonstrates a novel solenoid driver circuit to generate an accurate H-field by comparing digital and analog approaches and comparing the experimental data with the theoretical data.
    Preview · Article · Nov 2003
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    H. Hashempour · F.J. Meyer · F. Lombardi · F. Karimi
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    ABSTRACT: Not Available
    Full-text · Conference Paper · Jan 2003
  • F. Karimi · F.J. Meyer · F. Lombardi
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    ABSTRACT: This paper presents the analysis and modeling of random testing for its application to multi-port memories. Ports operate to simultaneously test the memory and detecting multi-port related faults. The state of the memory under test in the presence of inter-port faults has been modeled using Markov state diagrams. In the state diagrams, transition probabilities are established by considering the effects of the memory operations (read and write), the lines involved in the fault (bit and word-lines) as well as the types and number of ports. Test lengths per cell at 99.9% coverage are given.
    No preview · Conference Paper · Feb 2002
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    A. Choi · N. Park · F.J. Meyer · F. Lombardi · V. Piuri
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    ABSTRACT: Advances in spaceborne vehicular technology have made possible the long-life duration of the mission in harsh cosmic environments. Reliability and data integrity are commonly emphasized requirements of spaceborne solid-state mass storage systems, because faults due to the harsh cosmic environments - such as extreme radiation - can be experienced throughout the mission. Acceptable dependability for these instruments have been achieved by using redundancy and repair. Reconfiguration (repair) of memory arrays using spare memory lines is the most common technique for reliability enhancement of memories with faults. Faulty cells in memory arrays are known to show spatial locality. This physical phenomenon is referred to as fault clustering. This paper initially investigates a quadrat-based fault model for memory arrays under clustered faults to establish a sound foundation of measurement. Then, long-life dependability of a fault-tolerant spaceborne memory system with hierarchical active redundancy, which consists of spare columns in each memory module and redundant memory modules, is measured in terms of reliability (i.e., the conditional probability that the system performs correctly throughout the mission) and mean-time-to-failure (MTTF i.e., the expected time that a system will operate before it fails).
    Full-text · Conference Paper · Feb 2002
  • H. Hashempour · F.J. Meyer · F. Lombardi
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    ABSTRACT: This paper analyzes an environment which utilizes Built-In Self-Test (BIST) and Automatic Test Equipment (ATE), to reduce the overall time for manufacturing test of complex digital chips. This requires properly establishing the time to switch front BIST to ATE (referred to us switchover time), thus utilizing ATE generated vectors to finally achieve the desired level of fault coverage. For this environment we model fault coverage us a function of the testability of the circuit under test and the numbers of vectors which are supplied by the BIST circuitry and the ATE. A novel approach is proposed: this approach is initially bused on fault simulation using a small set of random patterns: art estimate of the so-called detection profile of the circuit under test is established us basis of the test model. This analytical model effectively relates the testable features of the circuit under test to detection using both BIST and ATE us related testing processes.
    No preview · Conference Paper · Feb 2002
  • Jun Zhao · F.J. Meyer · F. Lombardi
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    ABSTRACT: Testing multimodule systems presents several challenges, particularly when systems use submicron technology. The authors propose strategies to diagnose interconnect faults in bus-structured systems using several models. We propose several methods and strategies for a diagnosis using different fault models, including those applicable to submicron technology. Besides defining new features, such as the logical extent of faults, we also propose a reduction strategy that permits 100% fault detection and identification (including fault location)
    No preview · Article · Feb 2002 · IEEE Design and Test of Computers
  • M. Choi · N. Park · F.J. Meyer · F. Lombardi
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    ABSTRACT: Performance and reliability are two of the most crucial issues in today's high-performance instrumentation and measurement systems. Instrumentation and measurement systems have found and enjoyed their performance enhancement through parallel and distributed processing. High speed and density Multistage Interconnection Networks (MINs) are widely-used subsystems of parallel processing and communication systems. New performance models are proposed to evaluate the fault tolerant MIN in this paper, thereby establishing a sound foundation for assuring the performance and reliability of fault tolerant MINs with high confidence level during parallel instrumentation. A concurrent fault detection and recovery scheme for MINs is introduced to enable a generic approach to fault tolerance by rerouting over the redundant interconnection links. A switch architecture to realize the concurrent testing and diagnosis is shown. The proposed performance models are developed and used to evaluate the compound effect of the fault tolerant operations such as testing, diagnosis and recovery on the throughput and delay. Results are shown on single transient and permanent stuck-at fault on links and storage units in switching elements. it is shown that the performance degradation for the overhead due to the fault tolerance is quite graceful while the performance degradation without fault recovery is unacceptable.
    No preview · Conference Paper · Feb 2002
  • J. Zhao · F.J. Meyer · N. Park · F. Lombard
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    ABSTRACT: We examine diagnosis of processor array systems formed as two-dimensional grids, with boundaries, and either four or eight neighbors for each interior processor. We employ a parallel test schedule. Neighboring processors test each other and report the results. Our diagnostic objectives is to find a fault-free processor or set of processors. The system may then be sequentially diagnosed by repairing those processors tested faulty according to the identified fault-free set. We establish an upper bound on the maximum number of faults that can be sustained without invalidating the test results under worst case conditions. We give test schedules and diagnostic algorithms that meet the upper bound as far as the highest order term. We compare these near optimal diagnostic algorithms to alternative algorithms-both new and already in the literature.
    No preview · Article · Nov 2001 · IEICE Transactions on Information and Systems
  • Jun Zhao · F.J. Meyer · F. Lombardi
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    ABSTRACT: This paper presents new approaches for detection and diagnosis (with no confounding or aliasing) of interconnect faults (short, open and stuck-at) in a system consisting of multiple RAM chips connected through busses. These systems (referred to as a bus-connected multi RAM systems, or BCMRS) are characterized by multiple types of lines (bus and driver lines), disjoint busses (address and data) as well as by the presence of memories (whose number is given by D). Detection and maximal diagnosis are considered under a restricted fault model (short faults only) as well as a general fault model (all types of faults)
    No preview · Conference Paper · Feb 2000
  • F.J. Meyer · N. Park
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    ABSTRACT: The average new chip design already exceeds two million devices. Companies are racing to produce innovative systems-on-a-chip (SoC). Economic exigencies are mandating the re-use of core designs. These trends have led to new research concerns in SoC testing, SoC yield prediction, core interfacing, and intellectual property (IP) protection. In this work, we address design decisions associated with embedded cores that have defect-tolerant properties. Specifically, we address whether knowledge about the remainder of the chip would result in different core design decisions pertaining to yield
    No preview · Conference Paper · Feb 2000
  • Wenyi Feng · Xiaotao Chen · F.J. Meyer · F. Lombardi
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    ABSTRACT: A comprehensive approach is given to reconfigure field programmable gate arrays (FPGAs) with faults in the logic resources. Reconfiguration consists of a reassignment of the cells that takes into account the one-time programmable nature of the chip resources. The method alters neither the FPGA nor the fault-free design; so the effectiveness of the reassignment depends on the efficient use of routing resources in the fault-free design. Under a generalized architecture, the spare routing resources needed are obtained to bypass each faulty cell and reassign its functions to a spare (unused) cell. If every channel has as many spare trades as half the number of logic cell inputs and outputs, then any single faulty cell can be reassigned, thus yielding a successful chip reconfiguration. The proposed reassignment algorithm has an efficient execution, so it can be run while chips are programmed and tested on an assembly line. The number of calls to the routing software is at worst quadratic in the number of faulty cells, provided no backtracking is needed in the reassignment. Under some randomness assumptions, the average number of calls to the routing software is linear in the number of faulty cells. The proposed method is analyzed with benchmark circuits and simulation results are presented
    No preview · Conference Paper · Dec 1999
  • Xia-Tao Chen · Wenyi Feng · Jun Zhao · F.J. Meyer · F. Lombardi
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    ABSTRACT: Field-programmable gate arrays can suffer from a variety of faults, ranging from wire anomalies and defects to inoperative programmable connections. The solution to these faults depends on whether or not we are dealing with a reprogrammable FPGA or a one time programmable (OTP) FPGA. To correct faults, developers can reconfigure FPGAs such as those made by Xilinx and Altera by reprogramming. These devices can be programmed many times, for different designs and applications. Correcting faults in OTP FPGAs, such as those made by Actel is more difficult. For one thing, OTP FPGAs are based on antifuses. With an antifuse, the FPGAs configuration information has an initial (default) value that can be changed, but once changed cannot be restored. Therefore, the procedures to bypass faulty cells or faulty routing in an OTP FPGA must meet more stringent requirements than for reprogrammable FPGAs. The “Reconfiguration Approaches” sidebar describes two methods other researchers have tried. This article describes our approach to reconfiguring OTP FPGAs. We explain how we determine if reconfiguration is feasible, the algorithms we used, and the results of our experiments on a generic OTP FPGA model and a generic detail router
    No preview · Article · Dec 1999 · IEEE Micro
  • F.J. Meyer · F. Lombardi · J. Zhao
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    ABSTRACT: We examine the problem of identifying good processors in self-testing two-dimensional grid systems. The grids have boundaries (not wrap-around) and degree 8. Our diagnostic objective is to identify at least one fault-free processor. From this, at feast one faulty processor could be identified and it would be possible to sequentially diagnose the system by repeated repair. We establish an upper bound on the worst case maximum number of faults while still being able to meet the diagnostic goal with an ideal diagnosis algorithm. A straightforward ideal diagnosis algorithm would have exponential complexity and would involve 16 parallel rounds of processor testing. We give a test schedule with at most 6 parallel rounds of testing. This test schedule tolerates asymptotically as many faults as an ideal algorithm (by a constant factor). The new test schedule will also work for grids with degree 4, which have inferior diagnostic potential
    No preview · Conference Paper · Dec 1999
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    ABSTRACT: This approach uses the criterion of equivalent classes to establish the equivalence between two circuits and designs. Combining simulation and automatic test pattern generation, it exploits similarities among designs to assess logical equivalence quickly and reliably
    Full-text · Article · May 1999 · IEEE Design and Test of Computers
  • T. Liu · X.-T. Chen · F.J. Meyer · F. Lombardi
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    ABSTRACT: This paper presents a new approach to detecting faults in interconnects; the novelty of the proposed approach is that test generation and scheduling are established using the physical characteristics of the layout of the interconnect under test. This includes critical area extraction and a realistic fault model for a structural methodology. Physical layout information is used to model the adjacencies in an interconnect and possible bridge faults with a weighted graph, which is then analyzed to appropriately compact the tests and schedule their execution for (early) detection of bridge faults. Generation and compaction of the test vectors are accomplished by calculating node and edge weight heuristics from the weighted adjacency graph. Simulation has been performed for unweighted and weighted fault models. Results on random interconnects and the local interconnect of a commercially available field-programmable gate array are provided. The advantage of the proposed approach is that, on average, early detection of faults is possible using significantly fewer tests than with previous approaches. A further advantage is that it represents a realistic alternative to adaptive testing because it avoids costly on-line test generation, while still having a small number of vectors.
    No preview · Article · Apr 1999 · IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • Jun Zhao · F.J. Meyer · F. Lombardi
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    ABSTRACT: This paper presents an approach for the maximal diagnosis of all faults (stuck-at, open and short) in the interconnect of a random access memory (RAM); the interconnect includes data and address lines. This approach accomplishes maximal diagnosis under a complex model in which the lines in the interconnect of the RAM are involved in multiple faults simultaneously. The proposed algorithm (referred to as the Improved Maximal Diagnosis Algorithm, or IMDA) requires max{n,m-I}+n+3 WRITE and max{n,m}+2n READ, where n is the number of address lines and m is the number of data lines
    No preview · Conference Paper · Feb 1999