Meng-Ting Hsu

National Yunlin University of Science and Technology, Tou-liu, Taiwan, Taiwan

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Publications (26)5.52 Total impact

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    Meng-Ting Hsu · Kun-Long Wu · Wen-Chen Chiu

    Preview · Article · Jan 2015 · Wireless Engineering and Technology
  • Meng-Ting Hsu · Po-Hung Chen · Yao-Yen Lee
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    ABSTRACT: In this paper, a low-power CMOS LC voltage-controlled oscillator (VCO) with body-biasing and low-phase noise with Q-enhancement techniques is presented. A self-body biased circuit is introduced that can reduce power consumption. Some derivations of the Q-enhancement and how to improve the phase noise of the circuit are also discussed. This chip is implemented by the Taiwan Semiconductor Manufacture Company 0.18 µm 1P6M process. The measurement results exhibit a tuning range of 14.7% from 4.92 to 5.7 GHz at a supply voltage of 1.4 V. The power consumption of the core circuit and figure of merit are 2.5 mW and −188.6 dBc/Hz. The phase noise is −118 dBc/Hz@1 MHz at an operation frequency of 4.94 GHz.
    No preview · Article · Dec 2014 · International Journal of Microwave and Wireless Technologies
  • Meng-Ting Hsu · Yu-Hsien Lin · Yang Jing-Cheng
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    ABSTRACT: A low-power low-noise amplifier (LNA) utilized a resistive inverter configuration feedback amplifier to achieve the broadband input matching purposes. To achieve low power consumption and high gain, the proposed LNA utilizes a current-reused technique and a splitting-load inductive peaking technique of a resistive-feedback inverter for input matching. Two wideband LNAs are implemented by TSMC 0.18 μm CMOS technology. The first LNA operates at 2–6 GHz. The minimum noise figure is 3.6 dB. The amplifier provides a maximum gain (S21) of 18.5 dB while drawing 10.3 mW from a 1.5-V supply. This chip area is 1.028×0.921 mm2. The second LNA operates at 3.1–10.6 GHz. By using self-forward body bias, it can reduce supply voltage as well as save bias current. The minimum noise figure is 4.8 dB. The amplifier provides a maximum gain (S21) of 17.8 dB while drawing 9.67 mW from a 1.2-V supply. This chip area is 1.274×0.771 mm2.
    No preview · Article · Jul 2014 · Microelectronics Journal
  • Meng-Ting Hsu · Tsung-Han Han · Yao-Yen Lee
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    ABSTRACT: A CMOS LC voltage controlled oscillator (VCO) based on current reused topology with low phase noise and low power consumption is presented for IEEE 802.11a (Seller et al. A 10 GHz distributed voltage controlled oscillator for WLAN application in a VLSI 65 nm CMOS process, in: IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 3–5 June, 2007, pp. 115–118.) application. The chip1 is designed with the tail current-shaping technique to obtain the phase noise −116.1 dBc/Hz and power consumption 3.71 mW at the operating frequency 5.2 GHz under supply voltage 1.4 V. The second chip of proposed VCO can achieve power consumption Sub 1 mW and is still able to maintain good phase noise. The current reused and body-biased architecture can reduce power consumption, and better phase noise performance is obtained through raising the Q value. The measurement result of the VCO oscillation frequency range is from 5.082 GHz to 5.958 GHz with tuning range of 15.8%. The measured phase noise is −115.88 dBc/Hz at 1 MHz offset at the operation frequency of 5.815 GHz. and the dc core current consumption is 0.71 mA at a supply voltage of 1.4 V. Its figure of merit (FOM) is −191 dBc/Hz. Two circuits were taped out by TSMC 0.18 μm 1P6M process.
    No preview · Article · Jun 2014 · Microelectronics Journal
  • Meng-Ting Hsu · Yi-Cheng Chang · Yu-Zhang Huang
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    ABSTRACT: This paper presents two low power UWB LNAs with common source topology. The power reduction is achieved by the current-reused technique. The gain and noise enhancement of the proposed circuit is based on an output buffer which is used by a common source amplifier with shunt–shunt feedback. Chip1 is an adopted T-match input network of 50 Ω matching in the required band. Measurements show that the S11 and S22 are less than −10 dB, and the maximum amplifier gain S21 gives 9.7 dB, and the noise figure is 4.2 dB, the IIP3 is −8.5 dBm, and the power consumption is 11 mW from 1.1 V supply voltage. The input matching of chip2 is adopted from a LC high pass filter and source degenerated inductor. The output buffer with the RC-feedback topology can improve the gain, increase the IIP3, restrain the noise, improve the noise figure and decrease the DC power dissipation. Measurements show 13.2 dB of power gain, 3.33 dB of noise figure, and the IIP3 is −3.3 dBm. It consumes 9.3 mW from 1.5 V supply voltage. These two chips are implemented in a 0.18 μm TSMC CMOS process.
    No preview · Article · Dec 2013 · Microelectronics Journal
  • Meng-Ting Hsu · Yu-Hua Lin · Jing-Cheng Yang
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    ABSTRACT: This paper presents an UWB low noise amplifier (LNA) based on current reused and forward body-bias topology to achieve high figure of merit. The circuit was fabricated in a TSMC 0.18 μm CMOS process. The implemented LNA has a peak gain of 14.8 dB, the input reflection coefficient S11 is lower than -11.5 dB, and the output reflection S22 is lower than -10.7 dB, the minimum of the noise figure is 3.5 dB and the measurement of IIP3 is -13 dBm. It consumes 7.8mW power consumption from 1.1-V supply voltage. The figure of merit is 13.02.
    No preview · Conference Paper · Nov 2013
  • Meng-Ting Hsu · Po-Yu Lee · Yu-Zhang Huang
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    ABSTRACT: This paper proposed a active notch filter for an UWB low noise amplifier (LNA) in 0.18μm CMOS process. The measurement of the input and output reflection coefficient S11, S22 are less than -10 dB, the maximum power gain S21 gives 18.7dB, the minimum of the noise figure is 4.8dB, the measured IIP3 is -8.1dBm at 6GHz. It consumes 6.1mW power consumption from a 1-V supply voltage including the output buffer.
    No preview · Conference Paper · Oct 2013
  • Meng-Ting Hsu · Yu-Chang Hsieh · An-Cheng Ou
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    ABSTRACT: This paper presents a 3.1-10.6GHz low power and low noise amplifier(LNA) band on the cascode configuration. The circuit design consists of RC-feedback and forward body bias technique. The measurement results show the proposed UWB CS LNA can achieve a maximum power gain (S21) of 10.8dB with the 3dB bandwidth from 3.1GHz to 10.6GHz. The input reflection coefficient S11 and output reflection coefficient S22 are lower than -8.1dB and -9.5dB, respectively. A minimum noise figure of 5.5 dB, and an input third-order intercept point IIP3 of -6.4dBm. The power dissipation is 6.4mW at 1.1V supply voltage. This LNA occupies an area of 1.1*0.88mm2.
    No preview · Conference Paper · Oct 2013
  • Meng-Ting Hsu · Shih-Yu Hsu · Yu-Hwa Lin
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    ABSTRACT: This paper presents a low-power and low-noise amplifier (LNA) with resistive-feedback configuration. The design consists of two resistive-feedback amplifiers. In order to reduce the chip area, a resistive-feedback inverter is adopted for input matching. The output stage adopts basic topology of an RC feedback for output matching, and adds two inductors for inductive peaking at the high band. The implemented LNA has a peak gain of 10.5 dB, the input reflection coefficient S11 is lower than −8 dB and the output reflection S22 is lower than −10.8 dB, and noise figure of 4.2–5.2 dB is between 1 and 10 GHz while consuming 12.65 mW from a 1.5 V supply. The chip area is only 0.69 mm2 and the figure of merit is 6.64 including the area estimation. The circuit was fabricated in a TSMC 0.18 um CMOS process.
    No preview · Article · Feb 2013 · International Journal of Microwave and Wireless Technologies
  • Source
    Meng-Ting Hsu · Wei-Jhih Li · Chien-Ta Chiu
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    ABSTRACT: In this paper, we present low phase noise and low power of the modified current-reused VCOs for 10 GHz application. Three chips are implemented by the standard 0.18 μm CMOS process. The improvement of the VCOs' three chips is described step by step.The traditional current-reused circuit with a wide tuning range of 17.2% is presented in the first chip. It has a phase noise-118 dBc/Hz at 1 MHz offset and 5 mW core power dissipation with a voltage supply under 1.5 V. The performance of FOM is as high as −191.8 dBc/Hz. Extra NMOS cross-coupled pairs inside the traditional current-reused circuit in the second chip is proposed to speed up the oscillation and stability. The phase noise is −106.19 dBc/Hz and the core power dissipation is 3 mW with a voltage supply under 1.5 V. For the third chip, two dc level shifters are adopted to improve the symmetry of the output signal and to decrease noise interference. The phase noise and core power are -106.9 dBc/Hz and 2.88 mW, respectively. It also has a high performance of FOM with −182.4 dBc/Hz.
    Preview · Article · Feb 2013 · Microelectronics Journal
  • Meng-Ting Hsu · Yu-Tuan Hsu · Yao-Yen Lee
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    ABSTRACT: The paper presents a low power and low phase noise voltage controlled oscillator (VCO) for IEEE 802.11a applications. The quality enhancement and reducing current architecture is designed to improve phase noise and power. The measured results exhibited phase noise -115.62 dBc/Hz at 1MHz offset frequency and measured tuning range is about 14.5% from 5.26GHz to 6.08GHz. The power dissipation is 2.26mW and FOM is -187dBc/Hz. The chip fabrication of VCO is made by TSMC 0.18μm 1P6M CMOS standard process.
    No preview · Conference Paper · Jan 2013
  • Meng-Ting Hsu

    No preview · Article · Jan 2013 · Wireless Engineering and Technology
  • Meng-Ting Hsu · Wei-Jhih Li · Yu-Tuan Hsu
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    ABSTRACT: This paper presents a low phase noise wideband CMOS VCO based on the self-bias tail transistor technique and harmonic suppression using a capacitance ground. This VCO utilizes switching capacitor arrays in which four channels are able to be selected for multi-band application. Moreover, the design of CMOS VCO makes good use of the self-bias tail transistor and capacitance ground filter technique to reduce the phase noise. The MOS varactors are used as fine tuning for wideband operating application. The fully integrated VCO provides excellent performance with high FOM −193 dBc/Hz. The bandwidth of the frequency is 1.1 GHz and the tuning range is 13.8%. The power dissipation of the core circuit is 8.28 mW under a 1.8 V supply and phase noise is measured as low as −123.6 dBc/Hz at 1 MHz offset under 8.5 GHz oscillation frequencies. This VCO was made by the TSMC 0.18 μm 1P6M CMOS standard process and the chip area is 0.75×0.69 (mm2).
    No preview · Article · Jan 2013 · Microelectronics Journal
  • Source
    Meng-Ting Hsu · Jhih-Huei Du · Wen-Chen Chiu
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    ABSTRACT: This paper presents the design of a low power LNA with second stage that uses a notch filter for DS-UWB application. The LNA employs a current reuse structure to reduce the power consumption and an active second order notch filter to produce band rejection in the 5 -6 GHz frequency band. The input reflection coefficient S11 and output reflection S22 are both less than –10 dB. The maximum power gain S21 is 15 dB while the maximum rejection ratio is over –10 dB at 4.8 GHz. The minimum noise figure is 5 dB. The input referred third-order intercept point (IIP3) is –7 dBm at 6 GHz. The power consumption is 6.4 mW from a 1-V power supply.
    Preview · Article · Jan 2012 · Wireless Engineering and Technology
  • Meng-Ting Hsu · Yu-Hsien Lin
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    ABSTRACT: A low-power low-noise amplifier (LNA) utilizing resistive inverter configuration feedback amplifier to achieve the broadband input matching purposes, and used of self-forward-body-bias (SFBB) technique to further increase the gain of the whole frequency band and suppress the noise. By using the SFBB technique, it reduces supply voltage as well as saves additional bias circuit. This UWB LNA is implemented by TSMC 0.18µm CMOS technology. The minimum noise figure is 4.8 dB. The amplifier provides maximum gain (S21) of 17.8 dB while drawing 9.67mW from 1.2-V supply. This chip area is 1.274 × 0.771 mm2.
    No preview · Article · Jan 2011
  • Meng-Ting Hsu · Po-Hung Chen
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    ABSTRACT: A low power CMOS LC Voltage Controlled Oscillator (VCO) with body-biasing and Q-enhancement techniques is presented. This circuit was taped out by TSMC 0.18um 1P6M process. The measurement result of the VCO oscillation frequency range is from 4.92GHz to 5.7GHz, the tuning range of 14.7%. and the dc core current consumption is 1.78mA at a supply voltage of 1.4 V. The measured phase noise is −118dBc/Hz at 1MHz offset at the operation frequency of 4.94GHz.It achieves figure of merit (FOM) is −188.6dBc/Hz.
    No preview · Article · Jan 2011
  • Source
    Meng-Ting Hsu · Chien-Ta Chiu · Shiao-Hui Chen
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    ABSTRACT: This VCO presents a technique of operating narrowband into wideband, employs switching tail current technique and maintains the good phase noise performance. The switching capacitor modules offered multi-channels can enhance oscillator frequency range and the KVCO is still small. This VCO operated from 3.64 to 5.37 GHz with 38% tuning range. The power consumption is 13.7 mW by a 1.8 V supply voltage and measured phase noise in all tuning range is less than -122 dBc/Hz at 1 MHz offset.
    Preview · Chapter · Apr 2010
  • Meng-Ting Hsu · Shih-Yu Hsu
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    ABSTRACT: This paper presents a 1-10 GHz low power and low noise amplifier (LNA) with resistive-feedback configuration. The design consists of two resistive-feedback amplifier. In order to reduce the chip area, resistive-feedback inverter is adopt for input matching. The output stage adopt basic topology of a resistive feedback for output matching, and add two inductor for inductive peaking at high-band. The implemented LNA shows a peak gain of 10.5 dB, the input reflection coefficient S11 lower than -8 dB and output reflection S22 are lower than -10.8 dB, and NF of 4.2~5.2 dB between 1~10 GHz while consuming 12.65 mw through a 1.5 V supply. The chip was fabricated in TSMC 0.18 um CMOS process.
    No preview · Conference Paper · Jan 2010
  • Meng-Ting Hsu · Chien-Ta Chiu
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    ABSTRACT: This paper presents a low power 10 GHz voltage-controlled oscillator (VCO) with current reused topology and uses negative resistance enhancement technique. The proposed VCO operates from 9.08 GHz to 10.67 GHz with a tuning range of 16.1%. The VCO has a phase noise of -106.19 dBc/Hz at 1 MHz offset from 10.19 GHz oscillation frequency with 3 mW core power dissipation and 16.27 mW total power dissipation draw from a 1.5 V power supply. This VCO was made by TSMC 0.18 ¿m 1P6M CMOS standard process and the chip area is 0.505 × 0.573 (mm<sup>2</sup>).
    No preview · Conference Paper · Jan 2010
  • Meng-Ting Hsu · Shih‐Kai Lin
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    ABSTRACT: A CMOS low noise amplifier (LNA) for low-power ultra-wideband wireless applications is presented. To achieve low power consumption and wide operating bandwidth, the proposed LNA uses a current-reused technique and a simple high-pass input matching network. This work is implemented in 0.18-μm CMOS process technology and shows a 3.1–10.6 GHz bandwidth. With only 1.5 V supply voltage, the LNA can achieve power flat gain of 13.2 dB with input matching of −10.3 dB, the minimum noise figure of 3.33 dB, and input third-order-intercept point (IIP3) of −3.3 dBm. The power dissipation is only 9.3 mW. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 2077–2080, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24581
    No preview · Article · Sep 2009 · Microwave and Optical Technology Letters