Michele Ruo

Società Italiana di Medicina Generale, Florens, Tuscany, Italy

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Publications (2)0.32 Total impact

  • [Show abstract] [Hide abstract] ABSTRACT: . Lyfestiles, health and cardiovascular risk: the results of the study "Rischio & Prevenzione". The substantial agreement of the recommendations aimed to promote the so called "healthy lifestyle habits" dose not coincide to a rebut body of evidences on the transferability of the guidelines into daily conditions of care. The large cohort of ~12.000 patients included in a prospective-observational and experimental study conducted by a country-wide network of 860 Italian General Practitioners, provided the opportunity of testing the yield of the broad spectrum of life habits found across ages (>55 years, sex, regions, on the prognosis for fatal and not fatal events). While documenting and quantifying over the relative short period of time of the study (~ 4 years) the highly significant advantage of each of the components (diet and physical exercise) of the habits, as well as their combination, the study could be the sum as specifically important for two more general reasons: a) it is the general practice based documentation of the public health importance of recommendations in an adult old population; b) the instruments developed and tested to qualify-quantify the risk profiles are specifically praticabile in the busy setting of daily care.
    No preview · Article · Oct 2011 · Assistenza infermieristica e ricerca: AIR
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    [Show abstract] [Hide abstract] ABSTRACT: The Discrete Wavelet Transform (DWT) is a well-known mathematical tool, which has been proved to oer very good results for Digital Signal Processing applications. The DWT requires a massive computation, especially when real-time constraints are to be met, as it happens in a wide spectrum of applications; therefore dedicated processors are needed to achieve the necessary perfor-mance. In this paper a very high-speed VLSI implemen-tation of a two-dimensional DWT processor suitable for image processing is presented. The architecture is based on a bit-serial arithmetic; lin-ear systolic arrays are employed for row ltering and parallel arrays for column ltering. Each basic building block of the arrays has been designed using a True Sin-gle Phase Clocking logic, then a manual place and route of the derived cells has been carried out. The processor works at 500 MHz and occupies less than 50 mm 2 in a 0.7 m CMOS technology.
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