[Show abstract][Hide abstract] ABSTRACT: A new design approach to create an efficient high-performance JPEG-LS encoder is proposed in this paper. The proposed implementation
compresses the image data with the lossless mode of JPEG-LS. When the acquisition of precious content (image) is specified
to occur in real-time, then lossless compression is essential. Lossless compression is important to critical applications,
such as the acquisition of medical images and transmission of high-definition high-resolution images from space (satellite).
The contribution of the paper is to introduce an efficient pipelined JPEG-LS encoder, which requires significantly lower encoding
time than any other available JPEG-LS hardware or software implementation. The experimental results show that encoding is
performed as expected in high-speed, being able to serve real-time applications. This is the first time that a JPEG-LS implementation
offers such a high-speed encoding.
Full-text · Article · Dec 2008 · Journal of Real-Time Image Processing
[Show abstract][Hide abstract] ABSTRACT: This paper introduces an innovative design which implements a high-performance JPEG-LS encoder. The encoding process follows the principles of the JPEG-LS lossless mode. The proposed implementation consists of an efficient pipelined JPEG-LS encoder, which operates at a significantly higher encoding rate than any other JPEG-LS hardware or software implementation while keeping area small.
[Show abstract][Hide abstract] ABSTRACT: A design approach to create small-sized, high-speed implementations of the keyed-hash message authentication code (HMAC) is the focus of this article. The approach showed that the critical path can be further reduced by exploiting special properties of the included hash functions. A significant design effort was made to keep the area low. The experimental results showed that a negligible area penalty was introduce for achieving an increase in throughput up to 390% compared to the competing implementations. Finally, the design was fully tested and verified for the Xilinx Virtex-E FPGA family using a prototype board.
[Show abstract][Hide abstract] ABSTRACT: A design approach to create small-sized highspeed implementations of the keyed-hash message authentication code (HMAC) is presented. The proposed implementation can either operate in HMAC-MD5 and/or in HMAC-SHA1 mode. The proposed implementations do not introduce significant area penalty. However the achieved throughput presents an increase compared to commercially available IP cores that range from 30%-390%. The main contribution of the paper is the increase of the HMAC throughput to the required level to be used in modern telecommunication applications, such as VPN and the oncoming 802.11n