[Show abstract][Hide abstract] ABSTRACT: We report FDSOI devices with a 20nm gate length (LG) and 5nm spacer, featuring a 20% tensile strained Silicon-on-Insulator (sSOI) channel NFET and 35% [Ge] partially compressive strained SiGe-on-Insulator (SGOI) channel PFET. This work represents the first demonstration of strain reversal of sSOI by SiGe in short channel devices. At Vdd of 0.75V, competitive effective current (Ieff) reaches 550/340 μA/μm for NFET, at Ioff of 100/1 nA/μm, respectively. With a fully strained 30% SGOI channel on thin BOX (20nm) substrate and Vdd of 0.75V, PFET Ieff reaches 495/260 μA/μm, at Ioff of 100/1 nA/μm, respectively. Competitive sub-threshold slope and DIBL are reported. With the demonstrated advanced strain techniques and short channel performance, FDSOI devices can be extended for both high performance and low power applications to the 10nm node.
[Show abstract][Hide abstract] ABSTRACT: A 10nm logic platform technology is presented for low power and
high performance application with the tightest contacted poly pitch
(CPP) of 64nm and metallization pitch of 48nm ever reported in the
FinFET technology on both bulk and SOI substrate. A 0.053um2
SRAM bit-cell is reported with a corresponding Static Noise Margin
(SNM) of 140mV at 0.75V. Intensive multi-patterning technology
and various self-aligned processes have been developed with 193i
lithography to overcome optical patterning limit. Multi-workfunction
(WF) gate stack has been enabled to provide Vt tunability without the
variability degradation induced by channel dopants.
[Show abstract][Hide abstract] ABSTRACT: We report, for the first time, high performance Ultra-thin Body and Box (UTBB) FDSOI devices with a gate length (LG) of 20nm and BOX thickness (TBOX) of 25nm, featuring dual channel FETs (Si channel NFET and compressively strained SiGe channel PFET). Competitive effective current (Ieff) reaches 630μA/μm and 670μA/μm for NFET and PFET, respectively, at off current (Ioff) of 100nA/μm and Vdd of 0.9V. Excellent electrostatics is obtained, demonstrating the scalability of these devices to14nm and beyond. Very low AVt (1.3mV·μm) of channel SiGe (cSiGe) PFET devices is reported for the first time. BTI was improved >20% vs a comparable bulk device and evidence of continued scalability beyond 14nm is provided.
[Show abstract][Hide abstract] ABSTRACT: A first time rigorous experimental study of effective current (Ieff) variability in high-volume manufacturable (HVM) 14nm Silicon-On-Insulator (SOI) FINFETs is reported which identifies, threshold voltage (Vtlin), external resistance (Rext), and channel trans-conductance (Gm) as three independent sources of variation. The variability in Gm, Vtlin (AVT=1.4(n)/0.7(p) mV-μm), and Ieff exhibit a linear Pelgrom fit indicating local variations, along with non-zero intercept which suggests the presence of global variations at the wafer level. Relative contribution of Gm to Ieff variability is dominant in FINFETs with small number of fins (Nfin); however, both Gm and Rext variations dominate in large Nfin devices. Relative contribution of Vtlin remains almost independent of Nfin. Both n and p FINFETs show the above mentioned trends.
[Show abstract][Hide abstract] ABSTRACT: This work presents SOI finFETs with fin width (Dfin) scaled to sub 15nm. The process flow provides robust Dfin scaling as depicted by the universal electrostatic scaling of the DIBL and sub-threshold swing (SS). The high field long channel mobility drops by ~6% with Dfin scaling, however, DIBL and SS improves by ~1.5X and ~2X, respectively, for 20nm channel length n/pfinFETs. The effective current (Ieff) at fixed Ioff improves by ~20% and ~30% for p and n finFETs, respectively, with Dfin scaling.
[Show abstract][Hide abstract] ABSTRACT: Two FinFET fabrication processes are compared with simulation: the conventional fin-first process and the novel fin-last process. With the fin-last process, more longitudinal strain can be incorporated into the channel from source and drain SiGe stressor than fin-first. pFET mobility advantage is 15% at fully-strained condition and with silicon recess. Maintaining vertical junction uniformity is the main challenge for fin-last. However, its impact on parasitic resistance and capacitances are small. Vertical junction non-uniformity is improved with source and drain recess and doping optimization.
[Show abstract][Hide abstract] ABSTRACT: This chapter contains sections titled: Introduction Traditional CMOS Integration Processes High-k/Metal Gate Integration Processes Mobility Metal Electrodes and Effective Work Function Tinv Scaling and Impacts on Gate Leakage and Effective Work Function Ambients and Oxygen Vacancy-Induced Modulation of Threshold Voltage Reliability Conclusions References
[Show abstract][Hide abstract] ABSTRACT: The natural choice to achieve multiple threshold voltages (Vth) in fully-depleted devices is by choosing the appropriate gate workfunction for each device. However, this comes at the cost of significantly higher process complexity. The absence of a body contact in FinFETs and insensitivity to back-gate bias leaves the conventional channel doping approach as the most practical technique to achieve multiple Vth. This choice, however, introduces a variable that is usually not considered in the context of fully depleted devices. For the first time, we demonstrate a multiple Vth solution at relevant device geometries and gate pitch for the 22nm node. We investigated the impact of FinFET channel doping on relevant device parameters such as Tinv, mobility, electrostatic control and Vth mismatch. We also show that Vth extraction by the “constant current” method could mislead the DIBL analysis of devices with greatly different channel mobility.
[Show abstract][Hide abstract] ABSTRACT: High-performance strain-engineered ETSOI devices are reported. Three methods to boost the performance, namely contact strain, strained SOI (SSDOI) for NFET, and SiGe-on-insulator (SGOI) for PFET are examined. Significant performance boost is demonstrated with competitive drive currents of 1.65mA/μm and 1.25mA/μm, and Ieff of 0.95mA/μm and 0.70mA/μm at Ioff =100nA/μm and VDD of 1V, for NFET and PFET, respectively.
[Show abstract][Hide abstract] ABSTRACT: Two implantation based schemes were explored for ETSOI NFET devices targeted for the 20 nm node. Amorphization of the thin SOI is a key issue for the implant pre RSD scheme. This can be alleviated by implanting through liner. Variability is the key issue for the implant post RSD scheme which can be alleviated by good process controls and by the use of a two step epitaxy scheme.
[Show abstract][Hide abstract] ABSTRACT: FinFET devices achieving N/P Ion values of 1250/950 uA/um at 100 nA/um at 1V, 1300/1000 uA/um with self-heating correction, are demonstrated, using a dual work function gate-first process flow at 100 nm gate pitch and 40 nm fin pitch. Ring-oscillator (RO, FO = 3) functionality has been demonstrated, showing excellent Vdd scalability. We have also demonstrated logic scan chain functionality and yield improvement by optimizing the gate stack process. An optimized SIT process has been developed to improve short-channel characteristics in devices with a small number of fins in a narrow active area, which is also critical for manufacturability improvement. Various conformal doping techniques for NFET/PFET are optimized to improve device performance.
[Show abstract][Hide abstract] ABSTRACT: Tungsten-based full metal gate (FMG) stacks that are equivalent to or better than metal-inserted poly-Si (MIPS) stack have been developed. These fully encapsulated FMG stacks enable borderless source/drain contacts needed for the 14 nm technology node and beyond, where the contacted gate pitch is expected to be less than 80 nm. Tungsten replaces gate salicidation with the sheet resistance ≤ 14 Ω/□. FMG stack show excellent Tinv scaling (0.92 and 1.15 nm for NFET and PFET, respectively) and enhanced hole mobility by 20% compared to MIPS gate stack. Fully integrated short channel devices and borderless contacts are demonstrated at 80 nm contacted gate pitch.
[Show abstract][Hide abstract] ABSTRACT: We present a detailed study of back bias (Vbb) impact on UTBB devices with a gate length (LG) of 25nm and BOX thicknesses (TBOX) of 25nm and 10nm, respectively. It is reported for the first time that the Vt is modulated by Vbb across a wide temperature range, from -40°C to 125°C. The device electrostatics and reliability, under various V bb are investigated. The short channel effect (SCE) is well maintained across the bias points. NFET GIDL and HCI both improve when negative bias is applied. The Vbb effect on ring oscillators' (ROs) performance, based on 100nm contacted gate pitch (CPP), and on a 0.08μm 2 6-T SRAM, based on 80nm CPP, are reported for the first time. Clear RO performance/leakage tradeoff and SRAM static noise margin (SNM) modulation by Vbb are observed. SNM of 206mV is achieved at Vdd=0.9V.
No preview · Article · Jan 2011 · Digest of Technical Papers - Symposium on VLSI Technology
[Show abstract][Hide abstract] ABSTRACT: For the first time we report extremely thin SOI (ETSOI) CMOS with 22 nm gate length (LG) and sub-100 nm contacted gate pitch for system-on-chip (SoC) applications. Multi-Vt transistors are demonstrated with competitive drive currents (NFET/PFET) of 1150/1050 μA/μm at Ioff = 100 nA/μm for high performance (HP) and 920/880 μA/μm at Ioff = 1 nA/μm for low power (LP), respectively, at VDD = 1 V. High density 6-T SRAM cells down to 0.08 μm2 are demonstrated. Compared with a 28nm bulk LP technology, the high drive currents of ETSOI transistors coupled with large capacitance reduction by aggressive LG scaling result in 25% improvement in ETSOI ring oscillator (RO) speed. Auxiliary ETSOI devices including epitaxy resistors with high precision and gated diodes with near ideal characteristics are fabricated to complete device menu for early ETSOI SoC design.