David Blaauw

University of Michigan, Ann Arbor, Michigan, United States

Are you David Blaauw?

Claim your profile

Publications (471)239.62 Total impact

  • [Show abstract] [Hide abstract]
    ABSTRACT: We present an 8-bit sub-ranging SAR ADC designed for bursty signals having long time periods with small code spread. A modified capacitive-DAC (CDAC) saves previous sample's MSB voltage and reuses it throughout subsequent conversions. This prevents unnecessary switching of large MSB capacitors as well as conversion cycles, reducing energy consumed in the comparator and digital logic and yielding total energy savings of 2.6×. In 0.18μm CMOS, the ADC consumes 120nW at 0.6V and 100kS/s with 46.9dB SNDR.
    No preview · Article · Feb 2016
  • [Show abstract] [Hide abstract]
    ABSTRACT: As we show in this paper, I/O has become the limiting factor in scaling down size and power toward the goal of invisible computing. Achieving this goal will require composing optimized and specialized-yet reusable-components with an interconnect that permits tiny, ultra-low power systems. In contrast to today's interconnects which are limited by power-hungry pull-ups or high-overhead chip-select lines, our approach provides a superset of common bus features but at lower power, with fixed area and pin count, using fully synthesizable logic, and with surprisingly low protocol overhead. We present MBus, a new 4-pin, 22.6 pJ/bit/chip chip-to-chip interconnect made of two "shoot-through" rings. MBus facilitates ultra-low power system operation by implementing automatic power-gating of each chip in the system, easing the integration of active, inactive, and activating circuits on a single die. In addition, we introduce a new bus primitive: power oblivious communication, which guarantees message reception regardless of the recipient's power state when a message is sent. This disentangles power management from communication, greatly simplifying the creation of viable, modular, and heterogeneous systems that operate on the order of nanowatts. To evaluate the viability, power, performance, overhead, and scalability of our design, we build both hardware and software implementations of MBus and show its seamless operation across two FPGAs and twelve custom chips from three different semiconductor processes. A three-chip, 2.2 mm(3) MBus system draws 8 nW of total system standby power and uses only 22.6 pJ/bit/chip for communication. This is the lowest power for any system bus with MBus's feature set.
    No preview · Article · Feb 2016
  • [Show abstract] [Hide abstract]
    ABSTRACT: We present a low power on-chip oscillator for system-on-chip designs. The oscillator introduces a resistive frequency locking loop topology where the equivalent resistance of a switched-capacitor is matched to a temperature-compensated resistor. The approach eliminates the traditional comparator from the oscillation loop, which consumes significant power and limits temperature stability in conventional relaxation oscillators. The oscillator is fabricated in 0.18μm CMOS and exhibits 27.4ppm/°C and <7ppm long-term stability while consuming 99.4nW at 70.4 kHz.
    No preview · Article · Feb 2016
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents a complete, autonomous, wireless temperature sensor, fully encapsulated in a 10.6mm(3) volume. The sensor includes solar energy harvesting with an integrated 2 μAh battery, optical receiver for programming, microcontroller and memory, 8GHz UWB transmitter, and miniaturized custom antennas with a wireless range of 7 meters. Full, stand-alone operation was demonstrated for the first time for a system of this size and functionality.
    No preview · Article · Feb 2016
  • [Show abstract] [Hide abstract]
    ABSTRACT: In this work, a switched-capacitor voltage regulator (SCVR) that dithers flying capacitance to reduce output voltage ripple is presented, and the benefits of such ripple reduction are investigated. In the proposed technique, SC converters are designed to run at the maximum available frequency, and the flying capacitance for different phases is adjusted according to load current change through comparators and a digital controller. The proposed technique is demonstrated in a 65 nm test chip consisting of a 40-phase SCVR with 4b capacitance modulation (CM) and a 2:1 conversion ratio. On-chip circuits for ripple measurement and load performance monitoring were included to accurately assess the magnitude and impact of ripple reduction. Measurement results show that at a 2.3 V input, an on-chip ripple magnitude of 6–16 mV at 1 V output is achieved for 11–142 mA load. Peak efficiency is 70.8% at a power density of [Formula: see text] .
    No preview · Article · Jan 2016 · IEEE Journal of Solid-State Circuits
  • Suyoung Bang · David Blaauw · Dennis Sylvester
    [Show abstract] [Hide abstract]
    ABSTRACT: A fully integrated successive-approximation (SAR) switched-capacitor (SC) DC–DC converter is presented that overcomes the coarse output voltage resolution limitation of traditional SC converters. An SAR SC converter cascades multiple stages of 2:1 SC converters, and achieves a fine-grained conversion ratio resolution of VIN/2N , where VIN is the input voltage and N is the number of stages. As the SAR SC converter generates the output voltage through SAR, each stage of 2:1 SC converter provides a fixed voltage level, requiring minimal configuration change for regulation. Analysis shows that the SAR SC converter has a slow-switching-limit output impedance increasing proportionally to [Formula: see text] (number of resolution), and switching loss of bottom-plate parasitic capacitor decreasing with the number of stages. As a test chip, an SAR SC converter with 7-b resolution is fabricated in 180 nm CMOS process and implemented by cascading 4:1 and five 2:1 two-phase interleaving SC stages. It achieves 31.25 mV voltage resolution with output voltages over 0.4 V at [Formula: see text] . Using this fine grain voltage regulation approach, line and load regulations are implemented with a feedback/feedforward controller with peak efficiency of 72% for load currents from [Formula: see text] . The test chip occupies [Formula: see text] and utilizes on-chip capacitors of 2.24 nF in total.
    No preview · Article · Jan 2016 · IEEE Journal of Solid-State Circuits
  • [Show abstract] [Hide abstract]
    ABSTRACT: A 5.58 nW real-time clock using a crystal oscillator is presented. In this circuit, the amplifier used in a traditional circuit is replaced with pulsed drivers. The pulse is generated with precise timing using a DLL. With this approach, an extremely low oscillation amplitude of 160 mV results in low-power operation. This low-amplitude oscillation is sustained robustly using additional supply voltages: a lower supply for the final drive stage and a higher supply used for pulses that drive the final drive stage, which ensures low ON-resistance necessary for reliable operation. The different supply levels are generated on-chip by a switched capacitor network (SCN) from a single supply. The circuit has been tested at different supply voltages and temperatures. It shows a minimum power consumption of 5.58 nW and power supply sensitivity of 30.3 ppm/V over supply voltage of 0.94–1.2 V, without degrading the crystal’s temperature dependency: between [Formula: see text]. Moreover, its performance as a real-time clock has been verified by measurement of an Allan deviation of 1.16 ×10− 8.
    No preview · Article · Jan 2016 · IEEE Journal of Solid-State Circuits

  • No preview · Article · Jan 2016 · IEEE Journal of Solid-State Circuits
  • Inhee Lee · Dennis Sylvester · David Blaauw

    No preview · Article · Jan 2016 · IEEE Journal of Solid-State Circuits
  • [Show abstract] [Hide abstract]
    ABSTRACT: In this paper, approximate SRAMs are explored in the context of error-tolerant applications, in which energy is saved at the cost of the occurrence of read/write errors (i.e., signal quality degradation). This analysis investigates variation-resilient techniques that enable dynamic management of the energy-quality tradeoff down to the bit level. In these techniques, the different impacts of errors on quality at different bit positions are explicitly considered as key enabler of energy savings that are far larger than a simple voltage scaling. The analysis is based on the experimental results in an energy-quality scalable 28-nm SRAM and the extrapolation to a wide range of conditions through the models that combine the individual energy contributions. Results show that the joint adoption of multiple bit-level techniques provides substantially larger energy gains than individual techniques. Compared with the simple voltage scaling at isoquality, the joint adoption of these techniques can provide more than 2x energy reduction at negligible area penalty. Energy savings turn out to be highly sensitive to the choice of joint techniques, thus showing the crucial importance of dynamic energy-quality management in approximate SRAMs.
    No preview · Article · Jan 2016 · IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper explores the effectiveness of different knobs to dynamically trade energy consumption with output quality in approximate SRAMs for error-tolerant applications (such as video). Leveraging the different impact of errors on quality at most significant bit (MSB) and least significant bit (LSB) positions, energy savings higher than those provided by simple voltage scaling are enabled. Firstly, a comparison of two techniques, dual-𝑽𝑫𝑫 and LSB dropping, is carried out showing that the latter is preferable thanks to its intrinsic simplicity and more pronounced energy savings. Secondly, a selective Error Correction Code (ECC) technique which reuses the LSBs as check bits to protect MSBs is investigated. Measurements on a 28nm CMOS 32kb SRAM show that bit dropping and bit reuse achieve an energy reduction of up to 33% and 28%, compared to simple voltage scaling at iso-quality. When combined together, the two techniques achieve a better energy saving (40%) and a supply voltage reduction of about 100mV at iso-quality. Finally, guidelines to select the energy-optimal combination of the two techniques are provided for a given quality target.
    No preview · Conference Paper · Sep 2015
  • [Show abstract] [Hide abstract]
    ABSTRACT: This work presents an ultra-low-power oscillator designed for wake-up timers in compact wireless sensors. In a conventional relaxation oscillator, a capacitor periodically resets to a fixed voltage using a continuous comparator, thereby generating an output clock. The reset is triggered by a continuous comparator and thus the clock period is dependent on the delay of the continuous comparator which therefore needs to be fast compared to the period, making this approach power hungry. To avoid the power penalty of a fast continuous comparator, a constant charge subtraction scheme is proposed in this paper. As a constant amount of charge is subtracted for each cycle, rather than discharging/charging the capacitor to a fixed voltage, the clock period becomes independent of comparator delay. Therefore, the high power continuous comparator can be replaced with a coarse clocked comparator, facilitating low-power time tracking. For precise wake-up signal generation, an accurate continuous comparator is only enabled for one clock period at the end of the specified wakeup time. A wake-up timer using the proposed scheme is fabricated in a 0.18 µm CMOS process. The timer consumes 5.8 nW at room temperature with temperature stability of 45 ppm/°C (-10 °C to 90 °C) and line sensitivity of 1%/V (1.2 V to 2.2 V) .
    No preview · Article · Aug 2015 · IEEE Journal of Solid-State Circuits
  • [Show abstract] [Hide abstract]
    ABSTRACT: Indoor photovoltaic energy harvesting is a promising candidate to power millimeter (mm)-scale systems. The theoretical efficiency and electrical performance of photovoltaics under typical indoor lighting conditions are analyzed. Commercial crystalline Si and fabricated GaAs and Al0.2Ga0.8As photovoltaic cells were experimentally measured under simulated AM 1.5 solar irradiation and indoor illumination conditions using a white phosphor light-emitting diode to study the effects of input spectra and illuminance on performance. The Al0.2Ga0.8As cells demonstrated the highest performance with a power conversion efficiency of 21%, with open-circuit voltages >0.65 V under low lighting conditions. The GaAs and Al0.2Ga0.8As cells each provide a power density of nW/mm or more at 250 lx, sufficient for the perpetual operation of present-day low-power mm-scale wireless sensor nodes.
    No preview · Article · Jul 2015 · IEEE Transactions on Electron Devices
  • [Show abstract] [Hide abstract]
    ABSTRACT: A dual-slope capacitance-to-digital converter for pressure-sensing is presented and demonstrated in a complete microsystem. The design uses base capacitance subtraction with a configurable capacitor bank to narrow down input capacitance range and reduce conversion time. An energy-efficient iterative charge subtraction method is proposed, employing a current mirror that leverages the 3.6 V battery supply available in the system. We also propose dual-precision comparators to reduce comparator power while maintaining high accuracy during slope conversion, further improving energy efficiency. The converter occupies 0.105 mm$^{2}$ in 180 nm CMOS and achieves 44.2 dB SNR at 6.4 ms conversion time and 110 nW of power, corresponding to 5.3 pJ/conv-step FoM. The converter is integrated with a pressure transducer, battery, processor, power management unit, and radio to form a complete 1.4 mm$times$ 2.8 mm $times$ 1.6 mm pressure sensor system aimed at implantable devices. The multi-layer system is implemented in 180 nm CMOS. The system was tested for resolution in a pressure chamber with an external 3.6 V supply and serial communication bus, and the measured resolution of 0.77 mmHg was recorded. We also demonstrated the wireless readout of the pressure data on the stack system operating completely wirelessly using an integrated battery.
    No preview · Article · Jul 2015 · IEEE Journal of Solid-State Circuits
  • [Show abstract] [Hide abstract]
    ABSTRACT: Conventional Content Addressable Memory (BCAM and TCAM) uses specialized 10T / 16T bit cells that are significantly larger than 6T SRAM cells. We propose a new BCAM/TCAM that can operate with standard push-rule 6T SRAM cells, reducing array area by 2-5× and allowing reconfiguration of the CAM as an SRAM. Using a 6T 28nm FDSOI SRAM bit cell, the 64×64 (4kb) BCAM achieves 370 MHz at 1V and consumes 0.6fJ/search/bit.
    No preview · Conference Paper · Jun 2015
  • [Show abstract] [Hide abstract]
    ABSTRACT: This work proposes an area-efficient approach to fully exploit redundancy in reconfigurable sense amplifiers (SAs). The proposed SA can combine/invert offsets of sub-unit SAs, reducing offset by up to 3.1× at iso-area in 28nm FDSOI.
    No preview · Conference Paper · Jun 2015
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents an all-digital multiplying delay-locked loop (MDLL) with a leakage-based oscillator for ultra-low-power sensor platforms. The proposed digital control of channel leakage current achieved ultra-low-power consumption in frequency generation with a fine resolution. The leakage based oscillator was modeled as an RC-based oscillator, analyzed, and the analyses were verified by simulation. The proposed oscillator was applied to the MDLL with a fast frequency relocking scheme which adaptively performs an optimal lock process according to the amount of frequency drift during the sleep state. The MDLL was implemented in 65 nm CMOS and consumed 423 nW for 3.2 MHz generation, and had an energy efficiency FoM of 0.132 W/MHz.
    No preview · Article · May 2015 · IEEE Journal of Solid-State Circuits
  • [Show abstract] [Hide abstract]
    ABSTRACT: In this paper, a voltage-scaled SRAM for both error-free and error-tolerant applications is presented that dynamically manages the energy/quality trade-off based on application need. Two variation-resilient techniques, write assist and Error Correcting Code, are selectively applied to bit positions having larger impact on the overall quality, while jointly performing voltage scaling to improve overall energy efficiency. The impact of process variations, voltage and temperature on the energy-quality tradeoff is investigated. A 28 nm CMOS 32 kb SRAM shows 35% energy savings at iso-quality and operates at a supply 220 mV below a baseline voltage-scaled SRAM, at the cost of 1.5% area penalty. The impact of the SRAM quality at the system level is evaluated by adopting a H.264 video decoder as case study.
    No preview · Article · May 2015 · IEEE Journal of Solid-State Circuits
  • K. Yang · Q. Dong · D. Blaauw · D. Sylvester
    [Show abstract] [Hide abstract]
    ABSTRACT: Security is a key concern in today's mobile devices and a number of hardware implementations of security primitives have been proposed, including true random number generators, differential power attack avoidance, and chip-ID generators [1-4]. Recently, physically unclonable functions (PUFs) were proposed as a secure method for chip authentication in unsecure environments [5-7]. A PUF is a function that maps an input code ('challenge') to an output code ('response') in a manner that is unique for every chip. PUFs are increasingly used for IC authentication to offer protection against identity theft, cloning, and counterfeit components [2-4].
    No preview · Article · Mar 2015 · Digest of Technical Papers - IEEE International Solid-State Circuits Conference
  • W. Lim · I. Lee · D. Sylvester · D. Blaauw
    [Show abstract] [Hide abstract]
    ABSTRACT: Recent low-voltage design techniques have enabled dramatic improvements in miniaturization and lifetime of wireless sensor nodes [1-3]. These systems typically use a secondary battery to provide energy when the sensor is awake and operating; the battery is then recharged from a harvesting source when the sensor is asleep. In these systems, the key requirement is to minimize energy per operation of the sensor. This extends the number of operations on one battery charge and/or reduces the time to recharge the battery between awake cycles. This requirement has driven significant advances in energy efficiency [1-2] and standby power consumption [3].
    No preview · Article · Mar 2015 · Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Publication Stats

12k Citations
239.62 Total Impact Points

Institutions

  • 2001-2015
    • University of Michigan
      • • Division of Computer Science and Engineering
      • • Department of Electrical Engineering and Computer Science (EECS)
      Ann Arbor, Michigan, United States
  • 2002-2014
    • Concordia University–Ann Arbor
      Ann Arbor, Michigan, United States
  • 2012
    • Arizona State University
      Phoenix, Arizona, United States
  • 2009
    • ARM Ltd
      Cambridge, England, United Kingdom
  • 2005
    • Texas A&M University
      • Department of Electrical and Computer Engineering
      College Station, TX, United States
  • 2003-2005
    • University of Illinois, Urbana-Champaign
      Urbana, Illinois, United States
  • 2002-2003
    • The University of Arizona
      Tucson, Arizona, United States
  • 1997
    • Russian Academy of Sciences
      Moskva, Moscow, Russia
    • University of Texas at Austin
      Austin, Texas, United States