[Show abstract][Hide abstract] ABSTRACT: An 8 Gb 4-stack 3-D DDR3 DRAM with through-Si-via is presented which overcomes the limits of conventional modules. A master-slave architecture is proposed which decreases the standby and active power by 50 and 25%, respectively. It also increases the I/O speed to > 1600 Mb/s for 4 rank/module and 2 module/channel case since the master isolates all chip I/O loadings from the channel. Statistical analysis shows that the proposed TSV check and repair scheme can increase the assembly yield up to 98%. By providing extra VDD/VSS edge pads, power noise is reduced to < 100 mV even if all 4 ranks are refreshed every clock cycle consecutively.
No preview · Article · Feb 2010 · IEEE Journal of Solid-State Circuits
[Show abstract][Hide abstract] ABSTRACT: DRAMs in modules are preferably arranged in multiple ranks to increase system band-width. However, this limits the input/output (I/O) speed since increased channel loading causes degradation in signal integrity. To overcome the I/O speed limit, several buffered module solutions have been proposed, where data pins are buffered by additional chips. However, this increases power consumption and latency significantly. We present a 3D DRAM with TSVs that overcomes the limits of conventional module approaches. Important architectural aspects, and key 3D technologies such as inter-rank seamless read scheme, TSV check and repair scheme, and a power-noise reduction method are presented.