Lun-Yao Wang

Ningbo University, Ning-po, Zhejiang Sheng, China

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Publications (9)3.1 Total impact

  • Lun-Yao Wang · Zhu-Fei Chu · Yin-Shui Xia
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    ABSTRACT: Finite state machine (FSM) plays a vital role in the sequential logic design. In an FSM, the high peak current which is drawn by state transitions can result in large voltage drop and electromigration which significantly affect circuit reliability. Several published papers show that the peak current can be reduced by post-optimization schemes or Boolean satisfiability (SAT)-based formulations. However, those methods of reducing the peak current either increase the overall power dissipation or are not efficient. This paper has proposed a low power state assignment algorithm with upper bound peak current constraints. First the peak current constraints are weighted into the objective function by Lagrangian relaxation technique with Lagrangian multipliers to penalize the violation. Second, Lagrangian sub-problems are solved by a genetic algorithm with Lagrangian multipliers updated by the subgradient optimization method. Finally, a heuristic algorithm determines the upper bound of the peak current, and achieves optimization between peak current and switching power. Experimental results of International Workshop on Logic and Synthesis (IWLS) 1993 benchmark suites show that the proposed method can achieve up to 45.27% reduction of peak current, 6.31% reduction of switching power, and significant reduction of run time compared with previously published results.
    No preview · Article · Nov 2013 · Journal of Computer Science and Technology
  • Xian-jian Wang · Lun-yao Wang · Zhu-fei Chu · Yin-shui Xia
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    ABSTRACT: With the deficiency of the efficient of the Boolean SATisfiability (SAT) in the nano-meter CMOS circuit (CMOS/nanowire/MOLecular, CMOL) cell assignment resulted from the huge number of clauses and the big intermediate processing file, a novel approach using Pseudo-Boolean Satisfiability (PBS) to solve the CMOL cell assignment is proposed. The experimental results show that the proposed method can reduce the intermediate processing file efficiently by cutting down the number of the constraints without the additional Boolean variables introduced. The reduction of clauses and the intermediate processing file makes the proposed method work efficiently and improve the ability to deal with bigger circuits in contrast to the traditional SAT-based methods.
    No preview · Article · Oct 2013 · Dianzi Yu Xinxi Xuebao/Journal of Electronics and Information Technology
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    Zhufei Chu · Yinshui Xia · Lun-Yao Wang
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    ABSTRACT: Nanoelectronics constructed by nanoscale devices seems promising for the advanced development of integrated circuits (ICs). However, the lack of computer aided design (CAD) tools seriously hinders its development and applications. To investigate the cell mapping task in CAD flow, we present a genetic algorithm (GA) based method for Cmos/nanowire/MOLecular hybrid (CMOL), which is a nanohybrid circuit architecture. By designing several crossover operators and analyzing their performance, an efficient crossover operator is proposed. Combining a mutation operator, a GA based algorithm is presented and tested on the International Symposium on Circuits and Systems (ISCAS) benchmarks. The results show that the proposed method not only can obtain better area utilization and smaller delay, but also can handle larger benchmarks with CPU time improvement compared with the published methods.
    Preview · Article · Jan 2012 · Journal of Computer Science and Technology
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    ABSTRACT: Regarding the connectivity domain constraint in nano-meter circuit architecture, this paper proposes a circuit equivalent transformation method based on logic replication for reducing mapping complexity. The fanout degrees of all gates in a circuit are recorded and sorted to select the reference of high fanout value. Then a quadratic equation is formulated to evaluate whether the mapping complexities of the gates are reduced. Finally, the gate which has fanout degree larger than the reference high fanout value will be replicated if the complexity degree is reduced. The proposed method can not only make circuits easily to map, but also achieve better timing than buffer insertion.
    No preview · Article · Jul 2011 · Dianzi Yu Xinxi Xuebao/Journal of Electronics and Information Technology
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    ABSTRACT: By mapping a fixed polarity Reed-Muller (RM) expression into an onset table and studying the properties of the onset table, an algorithm is proposed to obtain a compact multi-level single-output mixed-polarity RM function by searching for and extracting the common variables using the onset table. Furthermore, by employing the multiplexer model, the algorithm is extended to optimize multi-level multi-output mixed-polarity RM forms. The proposed algorithm is implemented in C language and tested using some MCNC benchmarks. Experimental results show that the proposed algorithm can obtain a more compact RM form than that under fixed polarity. Compared with published results, the proposed algorithm makes a significant speed improvement, with a small increase in the number of literals. Key wordsLogic optimization–Reed-Muller functions–Multi-level–Mixed polarity–Onset table
    Preview · Article · Apr 2011 · Journal of Zhejiang University: Science C
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    ABSTRACT: This paper considers a cell mapping task of CMOL, a hybrid CMOS/molecular circuit architecture. To tackle the combinatorial hurdle arising from the structural connectivity domain constraint, a memetic computing algorithm is developed. The framework takes advantage of simulated annealing based local search strategy and appropriate population based encoding manipulation. Numerical results from ISCAS benchmarks and comparison with pure genetic approach illustrate the effectiveness of the modeling and solution methodology. In terms of CPU runtime, timing delay and circuit scale, the proposed method has better performance than previous methods.
    No preview · Conference Paper · Sep 2010
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    ABSTRACT: Reed-Muller logic is becoming increasingly attractive. However, its synthesis and optimization are difficult especially for mixed polarity Reed-Muller logic. In this paper, a function is expressed into a truth vector. Product shrinkage, general sum shrinkage (GSS), elimination and extraction operators are proposed to shrink the truth vector. A novel algorithm is presented to derive a compact Multi-level Mixed Polarity Reed-Muller Form (MMPRMF) starting from a given fixed polarity truth vector. The results show that a significant area improvement can be made compared with published results.
    Preview · Article · Oct 2005 · Journal of Computer Science and Technology
  • Yin-Shui Xia · Lun-Yao Wang · A. E. A. Almaini
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    ABSTRACT: A new CMOS quaternary D flip-flop is implemented employing a multiple-valued clock. PSpice simulation shows that the proposed flip-flop has correct operation. Compared with traditional multiple-valued flip-flops, the proposed multiple-valued CMOS flip-flop is characterized by improved storage capacity, flexible logic structure and reduced power dissipation.
    No preview · Article · Feb 2005 · Journal of Computer Science and Technology
  • Yinshui Xia · Xien Ye · Lun-Yao Wang · Zong-Gang Zhou

    No preview · Conference Paper · Jan 2005