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Conference Paper: A novel full coverage test method for CLBs in FPGA (abstract only).[Show abstract] [Hide abstract]
ABSTRACT: FPGA's configurability makes it difficult for FPGA's manufacturers to fully test it. In this paper, a full coverage test method for FPGA's Configurable Logic Blocks (CLBs) is proposed, through which all basic logics of FPGA's every CLB can be fully tested. Innovative test circuits are configured to build repeatable logic arrays for look-up tables, distributed random access memories, configurable registers and other logics. The programmable interconnects needed to connect CLBs in these test circuits are also repeatable, making the configuration process much easier and the test speed much faster. The test method is implemented on different scales of Xilinx Virtex chips, where 19 test configuration circuits are needed to achieve 100% coverage for all CLBs. Besides, the method is transplantable and independent of FPGA's array size. To evaluate the test method reliably and guide the process of test vectors generation, a fault simulator - Turbofault is used to simulate FPGA's test coverage.