Y.J. Lee

Northeastern University, Boston, Massachusetts, United States

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Publications (4)1.79 Total impact

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    ABSTRACT: The objective of this paper is to provide a framework by which jitter phenomena, which are encountered at the output signals of a head board in an automatic test equipment (ATE), can be studied. In this paper, the jitter refers to the one caused by radiated electromagnetic interference (EMI) noise, which is present in the head of all ATE due to DC-DC converter activity. An initial analysis of the areas of the head board most sensitive to EMI noise has been made. It identifies a sensitive part in the loop filler of a phase locked loop which is used to obtain a high frequency clock for the timing generator. Different H-fields are then applied externally at the loop filter to verify the behavior of the output signal of the head board in terms of RMS jitter. As for RMS jitter measurements, a frequency domain methodology has been employed. A trend for RMS jitter variation with respect to radiated EMI magnitude as well as frequency has been obtained. Also the orientation of the external H-field source with respect to the target board and its effects on the measured RMS jitter has been investigated. For measuring the RMS value, a proper circuitry has been designed on a daughter board to circumvent ground noise and connectivity problems arising from the head environment.
    Preview · Conference Paper · Jun 2004
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    ABSTRACT: This paper deals with the generation, measurement and modeling of the jitter encountered in the signals of a testhead board for automatic test equipment (ATE). A novel model is proposed for the jitter; this model takes into account the radiated electromagnetic interference (EMI) noise in the head of an ATE. The RMS value of the jitter is measured at the output signal of the testhead board to validate the proposed model. For measuring the RMS value, a novel circuitry has been designed on a daughter board to circumvent ground noise and connectivity problems arising from the head environment. An H-field is applied externally at the loop filter of a phase-locked loop (PLL), thus permitting the measurement of the RMS jitter to verify the transfer function between radiated EMI and jitter variation. The error between measured and predicted jitters is within a 15% level at both 200 kHz and 500 kHz.
    Preview · Article · Jan 2004 · IEEE Transactions on Instrumentation and Measurement
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    ABSTRACT: Recent research on modeling timing jitter has raised a requirement for a predictable, high magnitude, uniform, and wide bandwidth H-field. In this paper, a novel H-field generator design methodology is proposed. It consists of a single layer air core solenoid and a digital power switch driver that takes advantage of low power, wide bandwidth, and big current-driven capability. With input overdrive voltage, the digital switch can drive rail-to-rail voltage with output current up to 16A and power bandwidth more than 3 MHz. This paper demonstrates a novel solenoid driver circuit to generate an accurate H-field by comparing digital and analog approaches and comparing the experimental data with the theoretical data.
    Preview · Article · Nov 2003
  • YJ Lee · JJ Lim · YB Kim
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    ABSTRACT: This paper proposes a new clocking strategy for dynamic circuit. It provides faster performance and smaller area than conventional clocking scheme. The proposed clocking scheme for dynamic circuits provides the solution of the problem caused by logic polarity and clock skew problem simultaneously. To demonstrate the proposed clocking strategy, a 32 bit Carry Look Ahead adder (CLA) is designed and simulated using 0.25um CMOS technology to demonstrate 32.7% faster speed than the conventional clocking scheme and 19.4% transistor counter reduction.
    No preview · Conference Paper · Jan 2003

Publication Stats

10 Citations
1.79 Total Impact Points


  • 2003-2004
    • Northeastern University
      • Department of Electrical and Computer Engineering
      Boston, Massachusetts, United States