[Show abstract][Hide abstract] ABSTRACT: The implementation of devices with high mobility substrates requires growing III-V semiconductors over the underlying silicon substrates. However, due to the lattice mismatch, III-V materials tend to develop a significant density of structural defects, which may affect the device electrical characteristics. In this study, Threading Dislocation (TD) defects, which may propagate through the III-V layers, were studied using Conductive Atomic force Microscopy (CAFM). This technique is shown to be effective for identification and analysis at the nanoscale of the pre- and post-electrically stressed TD. The TD conduction studied at different temperatures (T) is shown to be consistent with the Poole-Frenkel (PF) emission process.
[Show abstract][Hide abstract] ABSTRACT: In this work, a simulator of conductive atomic force microscopy (C-AFM) was developed to reproduce topography and current maps. In order to test the results, the authors used the simulator to investigate the influence of the C-AFM tip on topography
measurements of polycrystalline high-k dielectrics, and compared the results with experimental data. The results show that this tool can produce topography images with the same morphological characteristics as the experimental samples under study. Additionally, the current at each location of the dielectric stack was calculated. The quantum mechanical transmission coefficient and tunneling current were obtained from the band diagram by applying the Airy wavefunction approach. Good agreement between experimental and simulation results indicates that the tool can be very useful for evaluating how the experimental parameters influence C-AFM measurements.
[Show abstract][Hide abstract] ABSTRACT: The implementation of high mobility devices requires growing III-V materials on silicon substrates. However, due to the lattice mismatch between these materials, III-V semiconductors tend to develop structural defects affecting device electrical characteristics. In this study, the CAFM technique is employed for identification and analysis of nanoscale defects, in particular, Threading Dislocations (TD), Stacking faults (SF) and Anti-phase Boundaries (APB), in III-V materials grown over silicon wafers.
[Show abstract][Hide abstract] ABSTRACT: The gallium nitride (GaN)-based buffer/barrier mode of growth and morphology, the transistor electrical response (25-310 °C) and the nanoscale pattern of a homoepitaxial AlGaN/GaN high electron mobility transistor (HEMT) have been investigated at the micro and nanoscale. The low channel sheet resistance and the enhanced heat dissipation allow a highly conductive HEMT transistor (Ids > 1 A mm(-1)) to be defined (0.5 A mm(-1) at 300 °C). The vertical breakdown voltage has been determined to be ∼850 V with the vertical drain-bulk (or gate-bulk) current following the hopping mechanism, with an activation energy of 350 meV. The conductive atomic force microscopy nanoscale current pattern does not unequivocally follow the molecular beam epitaxy AlGaN/GaN morphology but it suggests that the FS-GaN substrate presents a series of preferential conductive spots (conductive patches). Both the estimated patches density and the apparent random distribution appear to correlate with the edge-pit dislocations observed via cathodoluminescence. The sub-surface edge-pit dislocations originating in the FS-GaN substrate result in barrier height inhomogeneity within the HEMT Schottky gate producing a subthreshold current.
[Show abstract][Hide abstract] ABSTRACT: Resistive random access memories have raised as one of the most promising devices to store information due to their great yield and easy fabrication. In these cells, the memory concept is based on tuning the electrical resistance of the insulating layer in a metal-insulator-metal structure by applying electrical signals, so that a high resistive state (HRS or “0”) and a low resistive state (LRS or “1”) can be reached. Among all insulator candidates, hafnium oxides are the most preferred due to their good performance and compatibility with the existent microelectronic technology. It is widely known that the resistance switching (RS) mechanism in HfO2 stacks is based on the reversibility of the dielectric breakdown (BD), which is a local phenomenon that takes place in areas of ~100 nm2. Therefore, the use of electrical characterization tools with high spatial resolution is necessary to fully understand the conductivity changes in the dielectric. In this work, we use advanced nanoscale characterization tools to elucidate the origin of resistive switching in hafnium-based oxides.
Hafnium oxide thin films with different thicknesses and morphologies are analyzed using a Semiconductor Parameter Analyzer (SPA) connected to a Conductive Atomic Force Microscope (CAFM) working in controlled atmospheres (dry Nitrogen and a vacuum of 10-7 torr). Ramped Voltage Stresses have been performed at single locations of the samples to induce the formation of Conductive Filaments (CFs) - reach the dielectric breakdown (BD), or forming - . We analyze one-by-one the reversibility of those CFs, and we discern those locations where the BD could be recovered. Our experiments indicate that RS is only reachable at those filaments formed at the grain boundaries (GBs) of pseudo-amorphous and poly-crystalline samples (induced by thermal annealing), while the CFs induced at the nanocrystals or through the amorphous samples became irreversible (even using a current limitation). Kelvin Probe Force Microscope maps reveal that GBs are rich in defects, which correlates to larger leakage currents in (current maps) and lower BD voltages (forming, in IV curves). The lower BD voltages observed at the GBs (which, interestingly, coincide to those observed in MIM capacitors) may produce a less dramatic BD event, leading to narrower filaments easier to reoxidize. Moreover, the absolute value of the currents observed in LRS though a CF and a MIM structure are similar, indicating that RS in HfO2 stacks is a local phenomenon. This hypothesis is further supported by the fact that the currents through a CF in HRS and LRS can be fitted to the soft- and hard-BD equations. Finally we also show that, apart from creating/analyzing single CFs, the CAFM can also be used to perform statistical analyzes of the density, current and size of the CFs. In this case, two experiments are suitable to provide such information. The first consists of inducing the stresses in real capacitors, and scanning the surface of the insulator after etching the top electrode; and the second consists of collecting sequences of current maps at the same location of the sample using different voltages to observe a complete set-reset-set cycle. Since the maps cover larger areas and generate many filaments, this second test can be even combined with chemical analyses of lower spatial resolution.
In summary, CAFM experiments allow the correlation between nanoscale morphological features and electrical signals, and they can provide essential information to understand the origin of RS. In this work, CAFM studies experimentally in-situ proved, for the first time, that resistive switching in HfO2 stacks only takes place at the grain boundaries in polycrystalline samples due to an unusual high concentration of defects that minimize the violence of the BD event.
[Show abstract][Hide abstract] ABSTRACT: A new generation of non-volatile memories that store information
in a metal/insulator/metal cell with switchable electrical resistance
is gaining attention due to its simple structure and high yield.
Despite extensive device level measurements have been performed,
the origin of the resistive switching remains unclear. In this work,
we use a disruptive approach to characterize cyclic resistivity
changes at the nanoscale, combining a standard conductive atomic
force microscope and a semiconductor parameter analyzer. Using
this setup, we are able to assess the origin of resistive switching in
Hafnium-based oxides, which takes place at the grain boundaries
of polycrystalline stacks, and further calculations corroborate the
local nature of this phenomenon.
[Show abstract][Hide abstract] ABSTRACT: Conductive Atomic Force Microscopy (CAFM) has been demonstrated to be a very effective technique in providing detailed information on the morphological and electrical properties and failure mechanisms [1,2] of the gate dielectric of MOS devices from its characterization at the nanoscale. However, because of experimental difficulties, few efforts have been done to establish a correlation between the observed material properties and the electrical performance and reliability of electron devices. In this work, two case studies will be described to demonstrate that a well designed experiment, which combines standard electrical tests and CAFM measurements on the suitable test structures, can help in setting the nanoscale origin (technological and/or physical) of the observed device behavior. The impact of the poly-crystalline structure of a high-k material on the variability, performance, aging and TDDB of MOS structures has been analyzed. MOS capacitors with an Al gate electrode and a nominal 3.6nm thick HfO 2 film (grown by ALD) as gate dielectric were first considered. Before Al deposition, some of the samples were annealed at 350 o or 800 o C. Larger pre-BD currents and sample-to-sample variability and reduced reliability were observed on the 800 o C annealed structures (Figure 1) . Topography and current images were measured with the CAFM after removing the Al gate, on as-grown and CCS stressed devices. The sample annealed at 800 o C shows a granular structure (Fig.2.right), which has been attributed to the presence of randomly oriented nanocrystals (NC) separated by grain boundaries (GBs) . These samples also show larger inhomogeneities of the conductivity (larger rms current values), which considerably increases after stress (Table in Fig. 2) . All these results suggest that the polycrystallization of the high-k layer is an important source of device time-dependent variability. To further analyse this point, optimized HfO 2 stacks were fabricated. The nanoscale results demonstrate a clear correlation between topography and current (Fig. 3)  and contact potential difference (CPD) , showing larger currents and CPD (indicative of positive charge trapping) at the GBs. Moreover, under electrical stress, the GBs degrade faster than the grains (Fig. 4) and are preferential BD locations . Then, the higher initial currents at the GBs could be related to the higher concentration of positive charges there, likely associated with the segregation of positively charged oxygen vacancies. Larger voltages would be applied to the underlying SiO 2 interfacial layer at the GBs, leading to a faster degradation there, eventually leading to the BD of the entire stack . The nanoscale differences in the aging of MOSFETs after Bias Temperature Instability (BTI) and Channel Hot Carrier (CHC) Injection stresses have been evaluated on pMOSFETs (WxL=0,5µm x1µm) with a 1.4nm thick SiON layer as gate dielectric. After the BTI or CHC stress (Fig. 5), the layers on top of the gate dielectric were removed with a very selective wet etch, to expose the gate dielectric (Fig. 6). The CAFM current images (Fig. 7) suggest that (i) the number of leaky sites on the stressed MOSFETs is considerably larger and (ii) the distribution of leaky sites over the gate region depends on the kind of previous stress, being preferentially located close to the drain and source on the CHC pre-stressed MOSFETs (Fig. 8). TCAD simulations show that, under CHC stress, aging is caused by the combination of electric field and impact ionization effects (Fig. 8) , suggesting permanent damage caused by NBTI in the region close to source and hot-carrier injection close to the drain.
[Show abstract][Hide abstract] ABSTRACT: Dielectric breakdown (BD) in polycrystalline HfO2/SiO2 gate stacks has been studied using a conductive atomic force microscopy (CAFM) technique, which allows employing a nanosize probe to apply a highly localized electrical stress. The resulting BD statistics indicate that BD preferentially occurs in the interfacial SiO2 (IL) layer beneath the grain boundaries (GBs) of the overlaying polycrystalline HfO2 film due to higher conductivity of the GB compared to that of the grains.
No preview · Article · Mar 2013 · Microelectronic Engineering
[Show abstract][Hide abstract] ABSTRACT: Some high-k dielectric materials show two interchangeable conductivity states (a High Resistive State, HRS, and Low Resistive State, LRS) in what is known as Resistive Switching (RS), being the basis of ReRAMs. In this work, the Resistive Switching (RS) phenomenon is studied on ultrathin Hf based high-k dielectrics at the nanoscale, by using the conductive atomic force microscopy (CAFM), and at device level. The CAFM allows analysing the local dielectric properties of the RS phenomenon. At device level, the temperature dependence of the RS-related gate currents during the HRS and LRS has been studied in MOSFETs.
[Show abstract][Hide abstract] ABSTRACT: By combining electrical, physical, and transport/atomistic modeling results, this study identifies critical conductive filament (CF) features controlling TiN/HfO2/TiN resistive memory (RRAM) operations. The leakage current through the dielectric is found to be supported by the oxygen vacancies, which tend to segregate at hafnia grain boundaries. We simulate the evolution of a current path during the forming operation employing the multiphonon trap-assisted tunneling (TAT) electron transport model. The forming process is analyzed within the concept of dielectric breakdown, which exhibits much shorter characteristic times than the electroforming process conventionally employed to describe the formation of the conductive filament. The resulting conductive filament is calculated to produce a non-uniform temperature profile along its length during the reset operation, promoting preferential oxidation of the filament tip. A thin dielectric barrier resulting from the CF tip oxidation is found to control filament resistance in the high resistive state. Field-driven dielectric breakdown of this barrier during the set operation restores the filament to its initial low resistive state. These findings point to the critical importance of controlling the filament cross section during forming to achieve low power RRAM cell switching.
Full-text · Article · Dec 2012 · Journal of Applied Physics
[Show abstract][Hide abstract] ABSTRACT: AlGaN/GaN HEMTs are devices which are strongly influenced by surface properties such as donor states, roughness or any kind of inhomogeneity. The electron gas is only a few nanometers away from the surface and the transistor forward and reverse currents are considerably affected by any variation of surface property within the atomic scale. Consequently, we have used the technique known as conductive AFM (CAFM) to perform electrical characterization at the nanoscale. The AlGaN/GaN HEMT ohmic (drain and source) and Schottky (gate) contacts were investigated by the CAFM technique. The estimated area of these highly conductive pillars (each of them of approximately 20-50 nm radius) represents around 5% of the total contact area. Analogously, the reverse leakage of the gate Schottky contact at the nanoscale seems to correlate somehow with the topography of the narrow AlGaN barrier regions producing larger currents.
[Show abstract][Hide abstract] ABSTRACT: Resistive Switching (RS) phenomenon in Metal–Insulator–Metal (MIM) structures with polycrystalline HfO2 layers as dielectric has been studied at the nanoscale using Conductive Atomic Force Microscope (CAFM). The CAFM measurements reveal that (i) the conductive filaments (CFs) created at very small areas are the origin of the RS phenomenon observed at device level and (ii) RS conductive filaments are primarily formed at the grain boundaries, which exhibit especially low breakdown voltage. CAFM images obtained on MIM structures at the Low and High Resistive states also show that, although the current in the Low Resistive State is mainly driven by a completely formed single CF, the cell area dependence of the conductivity in the High Resistive State could be explained by considering the presence of multiple partially formed CFs.
No preview · Article · Sep 2012 · Microelectronics Reliability
[Show abstract][Hide abstract] ABSTRACT: The gate leakage current of AlGaN/GaN (on silicon) high electron mobility transistor (HEMT) is investigated at the micro and nanoscale. The gate current dependence (25–310 °C) on the temperature is used to identify the potential conduction mechanisms, as trap assisted tunneling or field emission. The conductive atomic force microscopy investigation of the HEMT surface has revealed some correlation between the topography and the leakage current, which is analyzed in detail. The effect of introducing a thin dielectric in the gate is also discussed in the micro and the nanoscale.
No preview · Article · Aug 2012 · Applied Physics Letters
[Show abstract][Hide abstract] ABSTRACT: The evolution over time of the leakage current in HfO2-based MIM capacitors under continuous or periodic constant voltage stress (CVS) was studied for a range of stress voltages and temperatures. The data were analyzed based on the results of conductive atomic force microscopy (AFM) measurements demonstrating preferential current flow along grain boundaries (GBs) in the HfO2 dielectric and ab initio calculations, which show the formation of a conductive sub-band due to the precipitation of oxygen vacancies at the GBs. The simulations using the statistical multi-phonon trap-assisted tunneling (TAT) current description successfully reproduced the experimental leakage current stress time dependency by using the calculated energy characteristics of the O-vacancies. The proposed model suggests that the observed reversible increase in the stress current is caused by segregation of the oxygen vacancies at the GBs and their conversion to the TAT-active charge state caused by reversible electron trapping during CVS.
No preview · Article · Nov 2011 · Solid-State Electronics
[Show abstract][Hide abstract] ABSTRACT: The evolution of the electrical properties of HfO2/SiO2/Si dielectric stacks under electrical stress has been investigated using atomic force microscope-based techniques. The current through the grain boundaries (GBs), which is found to be higher than thorough the grains, is correlated to a higher density of positively charged defects at the GBs. Electrical stress produces different degradation kinetics in the grains and GBs, with a much shorter time to breakdown in the latter, indicating that GBs facilitate dielectric breakdown in high-k gate stacks.
[Show abstract][Hide abstract] ABSTRACT: In this work, we combine conductive atomic force microscopy (CAFM) and first principles calculations to investigate leakage current in thin polycrystalline HfO2 films. A clear correlation between the presence of grain boundaries and increased leakage current through the film is demonstrated. The effect is a result of a number of related factors, including local reduction in the oxide film thickness near grain boundaries, the intrinsic electronic properties of grain boundaries which enhance direct tunnelling relative to the bulk, and segregation of oxygen vacancy defects which increase trap assisted tunnelling currents. These results highlight the important role of grain boundaries in determining the electrical properties of polycrystalline HfO2 films with relevance to applications in advanced logic and memory devices.
No preview · Article · Jul 2011 · Microelectronic Engineering
[Show abstract][Hide abstract] ABSTRACT: High-k dielectrics have been introduced in MOS devices to reduce gate leakage currents. However, their polycrystallization during a thermal annealing can affect the electrical properties and reliability of scaled devices. In this work, a Conductive Atomic Force Microscope (CAFM) has been combined with standard electrical characterization techniques at wafer level to investigate (I.) how the polycrystallization of a high-k layer affects its nanoscale morphological and electrical properties and (II.) how such nanoscale properties affect the electrical characteristics of fully processed devices. The impact of an electrical stress on the electrical conduction and charge trapping of amorphous and polycrystalline high-k layers has been also analyzed.
[Show abstract][Hide abstract] ABSTRACT: In this study, atomic force microscopy-related techniques have been used to investigate, at the nanoscale, how the polycrystallization of an Al2O3-based gate stack, after a thermal annealing process, affects the variability of its electrical properties. The impact of an electrical stress on the electrical conduction and the charge trapping of amorphous and polycrystalline Al2O3 layers have been also analyzed.
Full-text · Article · Jan 2011 · Nanoscale Research Letters
[Show abstract][Hide abstract] ABSTRACT: The relationship between the topographical and electrical properties of the polycrystalline HfO(2) layer has been investigated using conductive atomic force microscopy under ultrahigh vacuum conditions. Its high lateral resolution identified the grain boundaries (GBs) as a primarily conduction path through the dielectric. Electrical stress-induced breakdown sites were also found to be located at the GBs, suggesting that the polycrystalline phase of the gate dielectric may impair reliability. (c) 2011 American Vacuum Society. [DOI: 10.1116/1.3532945]
No preview · Article · Jan 2011 · Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures