B. Troyanovsky

Solido Design Automation, Inc., San José, California, United States

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Publications (14)2.96 Total impact

  • Boris Troyanovsky · Patrick O'Halloran · Marek Mierzwinski
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    ABSTRACT: Historically, compact transistor models have been developed using general- purpose programming languages such as C or Fortran, with the resulting source code specifically targeted to a given circuit simulator's proprietary model inter- face. Although this approach has allowed for the creation of robust and efficient compact models, it has nevertheless resulted in a situation where the model development process is lengthy, the models are not portable across the vari- ous simulation environments, and where the model development facilities are often not open to independent model developers. The advent of analog hardware description languages (AHDLs) over the last several years promises to address the aforementioned issues by providing a portable, robust, and efficient plat- form for analog model development. In this chapter, we describe the Verilog-A language and explore the numerous benefits it provides in the area of compact modeling.
    No preview · Chapter · Jan 2006
  • B. Troyanovsky · P. O'Halloran · M. Mierzwinski
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    ABSTRACT: Over the past several years, analog hardware description languages (AHDLs) have gained increasing acceptance in the areas of analog and RF circuit simulation. The widespread adoption of these standardized languages promises to bring substantial benefits to analog model developers and to the users of analog simulation tools. In this paper, we examine the applicability of the Verilog-A hardware description language for analog RF modeling tasks, with an emphasis on issues of importance to circuit designers, device modeling specialists, and simulation tool developers. The current capabilities and limitations, as well as future directions, are discussed.
    No preview · Conference Paper · Jul 2005
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    M Mierzwinski · Halloran · B Troyanovsky · K Mayaram · R Dutton
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    ABSTRACT: Historically, analog models and the simulators in which they are embedded form a single analog simulation kernel. This was true of SPICE and its predecessors and is true of most commercial and proprietary analog simulators in use today. As a consequence, while model interfaces generally serve the same function (allowing the model to define the differential equations of a system), the mechanics of each interface is specific to its simulator and the interface is complex and tightly interwoven with the analysis engine. Adding a new model to any analog simulator is a task that is measured in engineer-months requiring intimate knowledge of the simulator's architecture and, in some cases, thousands of lines of C code (BSIM4 is ~15k lines in SPICE3). Verilog-A, a language originally intended for behavioral modeling, has been shown to be a viable alternative to C-code [1-3] with comparable implementations typically providing an order of a magnitude reduction in the number of lines of code necessary. Acceptance of a model requires its availability in main-stream simulators. Simulation vendors generally do not add unproven, immature models because the return on investment is never guaranteed. For these reasons the cycle of analog model development and maturation has never flourished in analog CAD – an area of CAD where perhaps having accurate predictive models is most crucial. The capability of Verilog-A to describe compact model behavior in a concise and portable fashion can only be realized if commercial simulators incorporate the interface in a consistent way. In this paper we present simulation results using a new modular architecture implemented in both commercial and research simulators. We use industry standard models, including BSIMSOI and BSIM3, as well as MEMS models coupled into complex harmonic balance and device level simulators. This is the first demonstration of multiple commercial simulators sharing the same model binaries.
    Preview · Article · Jan 2004
  • Boris Troyanovsky · Zhiping Yu · Robert W. Dutton
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    ABSTRACT: Harmonic balance is a popular technique for simulating large-signal harmonic and intermodulation distortion in RF and microwave circuits. In this paper, we present algorithms which extend the applicability of harmonic balance to physics-based semiconductor device analysis. The algorithms presented here have been implemented in the PISCES-II device simulator, and have been used to simulate a wide variety of RF and microwave transistors embedded in realistic circuit networks containing biasing and parasitic elements. The simulator employs Krylov subspace solution techniques to solve the extremely large systems of equations arising in the context of two-dimensional device simulation. In the important case of multi-tone distortion problems, the size and density of the device Jacobian necessitate the introduction of novel preconditioning techniques (dubbed sectioned preconditioning) which exploit the special structure of the device simulation problem.
    No preview · Article · Jan 2000 · Computer Methods in Applied Mechanics and Engineering
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    R.W. Dutton · B. Troyanovsky · ZP Yu · T. Arnborg · F. Rotella · G. Ma · J. Sato-Iwanaga
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    ABSTRACT: The rapid growth of wireless systems at radio frequencies (RF) is driving the need for improved analog circuit and device analysis at gigaHertz frequencies. This includes: low noise front ends, linear amplifiers, mixers, and power amplifiers. Moreover, the parasitic effects of capacitance and inductance, both on- and off-chip, require careful extraction and characterization in support of predictive modeling. While time-domain techniques work well for digital systems, often the spectral and dynamic range requirements for communications systems necessitate accurate analysis of harmonic content with frequency differences of a thousandfold or more. This paper demonstrates the applicability and unique strengths of device-level harmonic balance (HB) in the simulation and physical modeling of RF circuits
    Preview · Conference Paper · Jan 1998
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    F.M. Rotella · Zhiping Yu · R. Dutton · B. Troyanovsky · G. Ma
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    ABSTRACT: This paper discusses a harmonic balance simulation involving a high power LDMOS device, bias circuitry and matching network. The paper begins with a discussion of the device and circuit configuration as well as the requirements for simulation. Next the paper describes the simulation algorithms and simulator structure in order to meet the requirements. PISCES is used as the basis and around it are added libraries for harmonic balance simulation and circuit boundary conditions. Finally, simulation results are presented. The experimental and simulated response of the power gain and power added efficiency of an RF power amplifier are shown
    Preview · Conference Paper · Oct 1997
  • N. Chang · L. Barford · B. Troyanovsky
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    ABSTRACT: The capability of time domain simulation with frequency domain data exists in some time-domain simulators, but the computations can be time-consuming. We decrease this computational burden by exploiting S-parameter fitter and fast recursive convolution methods. With recursive convolution the frequencies at which the S-parameters are sampled may be spaced in any way. For example, a logarithmic frequency spacing allows S-parameters to be sampled over a broader band without increasing the number of frequencies measured. We use two different system identification techniques for extracting the closed-form equations describing measured or simulated S-parameter data. Lumped parameter systems are approximated as a rational polynomial modulated by a complex exponential. Distributed parameter systems are approximated by the sum of complex exponentials. The recursive convolution engine handles both forms. The HP SPICE circuit simulator has been extended to allow fast, recursive convolution methods to be employed for transient analysis. The resulting simulator is called SSpice v2. Significant speed-up in the simulation of several circuits have been achieved using this new technique compared to both the traditional approach in SPICE and our previous direct-convolution-based approach in SSpice v1. In this paper, we present the algorithms and applications of the simulator. Three applications are demonstrated in the paper which are MR head flex line modeling, chip-to-chip signal modeling on MCM, and on-chip inductor modeling
    No preview · Conference Paper · Jun 1997
  • J. Sato-Iwanaga · K. Fujimoto · H. Masato · Y. Ota · K. Inoue · B. Troyanovsky · ZP Yu · R.W. Dutton
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    ABSTRACT: Distortion simulations of GaAs MESFETs based on a physical model and applying the harmonic balance method have been demonstrated. Simulation of circuit configurations with components such as blocking capacitors and RF chokes feeding 50 ohm terminations was performed. Good agreement has been obtained between simulation and measurements for harmonic distortion and two-tone intermodulation distortion characteristics.
    No preview · Conference Paper · Jan 1997
  • R.W. Dutton · B. Troyanovsky · Zhiping Yu · E.C. Kan · K. Wang · Tao Chen · T. Amborg
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    ABSTRACT: Capabilities for analog modeling of advanced transistors are demonstrated based on tools and techniques developed specifically to support technology development. In addition, providing support for more accurate analog modeling, there is the opportunity to predict technology dependencies and therefore to selectively target technology optimization for analog performance. The term “technology files” is well-known among circuit designers and specifically means the relevant circuit modeling information that contains technology dependencies. Technology computer-aided design (TCAD) provides powerful analog capabilities to directly predict not only the technology files but also a wide range of other critical behavior information about devices and circuits that depend directly on technology
    No preview · Conference Paper · Mar 1996
  • R.W. Dutton · ZP YU · F. Rotella · S. Beebe · B. Troyanovsky · L. So
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    ABSTRACT: A set of virtual instruments based on computer-aided design tools for technology (TCAD) are described. These virtual instruments support the evaluation of new technologies for circuit applications, including both intrinsic and parasitic effects. Mixed-mode (circuit/device) simulation in both the frequency and time-domain is demonstrated including an example of a virtual network analyzer applied to evaluation of a GaAs FET. Virtual curve-tracing is demonstrated as a powerful means to obtain I-V curves and to zoom in on the regions of device characteristics where SPICE model parameters can effectively be extracted and parasitic effects such as failure mechanisms due to electrostatic discharge (ESD) can be analyzed. Finally large signal distortion behavior analyzed based on the device simulation using the harmonic balance (HB) method is demonstrated with application to extraction of intermodulation (IM) distortion in bipolar transistor circuits
    No preview · Conference Paper · Jun 1995
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    Boris Troyanovsky · Zhiping Yu · Lydia So · Robert W. Dutton
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    ABSTRACT: Harmonic and intermodulation distortion effects play an important role in numerous analog applications, particularly in such areas as wireless communication systems. In this paper, we present a two-dimensional harmonic balance semiconductor device simulator which accurately models these nonlinear effects at the physical (drift-diffusion) level. The simulator is based on Stanford University's PISCES code, and supports the full range of physical models and features present in the time-domain version of the program. A modified block Gauss-Seidel-Newton nonlinear relaxation scheme is developed to efficiently handle the extremely large size of two-dimensional harmonic balance semiconductor device simulation problems
    Preview · Conference Paper · Jan 1995
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    B. Troyanovsky · Z. Yu · R. W. Dutton
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    ABSTRACT: Harmonic and interrnodiilation distortion effects play a key role in the de- sign and siibsequent performance of analog HF/pWave systems. Due to the wide range of frequency components present in such systems, ordinary transient analysis is both extremely time-consuming and insufficiently accurate. In this paper, we present a harmonic balance version of the PISCES semiconductor de- vice sim~ilator. This two-dimensional device simulation tool allows for efficier~t, physically-based analysis of intermod~ilation distortion in two-dimensional de- vice structures. Robust nonlinear relaxation methods have been developed to overcome the enorrnoiis memory and speed problems associated with fiilly- coupled, large-signal 2D frequency-domain analyses.
    Preview · Article · Jan 1995
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    Boris Troyanovsky

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  • M. Mierzwinski · P. O'Halloran · B. Troyanovsky · R. Dutton
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    ABSTRACT: Verilog-A has been demonstrated to be a suitable language to describe analog models (1). However, effective adoption by both the Electronic Design Automation (EDA) industry and end users requires that the language implementation provide all of the features and performance of C-coded models. A new architecture is proposed for implementing Verilog-A models in contemporary commercial simulators. The key components of the architecture are a stand-alone compiler that generates a dynamically linkable library and a run-time environment that is customized to particular simulators. The advantages of this architecture include an efficient distribution process, extendable support for existing and new analysis types, and fast execution. In this paper we present simulation results using this architecture implemented in several simulators. We use industry standard models, including BSIM3 and BSIM4, as a demonstration of complex models implemented in Verilog-A.
    No preview · Article ·