[Show abstract][Hide abstract] ABSTRACT: We have developed a cylindrical Ru/ST/Ru capacitor for gigabit-scale DRAMs. Using cylindrical CVD-Ru as a storage node (SN), a new 2-step CVD-ST was employed to improve ST step coverage, surface morphology and to control composition at the Ru/ST interface. A SiO<sub>2</sub> equivalent thickness (t<sub>eq</sub>) of 0.6 nm and cell capacitance of 18 fF/cell with leakage current of 0.1 fA/cell at ±0.7 V applied voltage has been achieved on a 256K cylindrical Ru/ST/Ru capacitor array
[Show abstract][Hide abstract] ABSTRACT: Ru films were fabricated by dc magnetron sputtering in an Ar/O2 mixture ambient in order to examine the Ru films as electrodes of Ba0.5Sr0.5TiO3 (BST) thin-film capacitors. The 100-nm-thick Ru film deposited on Si at 450°C at an O2/(Ar+O2) flow ratio of 40% at 0.5 kW was textured along c-axis. The full-width at half maximum (FWHM) of 3.14° was obtained for the Ru (002) diffraction peak in an X-ray diffraction (XRD) pattern. BST films deposited on the Ru bottom electrode were also textured along (110). The relative dielectric constant of BST films increased with a decrease in the FWHM of BST (110). The relationship between electrical properties of Ru/BST/Ru capacitors and the orientation of the Ru bottom electrode and BST films was also investigated.
No preview · Article · Nov 2000 · Japanese Journal of Applied Physics
[Show abstract][Hide abstract] ABSTRACT: A hot-wall batch type BST-CVD tool with fast thermal processing (FTP) furnace and individual vaporizing liquid source supply system (ILSS) was developed for uniform deposition of BST. We also employed an in-situ multi-step (IMS) process that is sequential repetition of thin amorphous BST deposition and its crystallization in the same reactor to reconcile conformal BST deposition and good electrical performances. BST deposited by our hot-wall CVD shows slight substrate dependence (metal coated or not), therefore hotwall CVD is superior to a single slice tool for reduction of test wafer running. IMS deposited BST shows almost 100% step coverage, lower carbon impurity concentration than single step deposited BST and sufficient electrical characteristics (leakage current <10<sup>-7</sup> A/cm<sup>2</sup>, Teq<0.5 nm) for both SRO and Ru electrodes.
[Show abstract][Hide abstract] ABSTRACT: We have developed low temperature SrTiO<sub>3</sub> (ST) capacitor
process for embedded DRAM. ST film deposited at 475°C was
crystallized without additional annealing. 0.53nm SiO<sub>2</sub>
equivalent thickness (teq) ST capacitor with Ru electrodes was obtained.
The leakage current of the concave structure capacitor was less than
1fA/cell at ±0.8V for 256K 3-dimensional (3D) capacitors
fabricated by the low temperature ST process. ST capacitor process can
satisfy demands on lower processing temperature and scalability to very
thin dielectric layer with low leakage current
[Show abstract][Hide abstract] ABSTRACT: Ru films were fabricated by chemical vapor deposition using Ru(C5H5)2 and O2.
The deposition of Ru film was controlled by the surface reaction kinetics as the rate limiting
step with activation energy of 2.48 eV below 250°C and by the mass transport process
above 250°C. Ru films had a polycrystalline structure and showed low resistivity of about
12 µΩcm. Ru films deposited at 230°C showed excellent step coverage. We applied Ru
films prepared by chemical vapor deposition to the bottom electrode of a Ba0.25Sr0.75TiO3
capacitor and obtained good electrical characteristics.
No preview · Article · Apr 1999 · Japanese Journal of Applied Physics
[Show abstract][Hide abstract] ABSTRACT: We developed a new in-situ multi-step (IMS) process technology to achieve both conformal step coverage and high dielectric constant for CVD-BST. IMS is a sequential repetition of low temperature CVD of BST and its crystallization in a batch type hot wall reactor that enables uniform BST deposition over 200 mm wafers. Conformal growth of local epitaxially grown BST with a dielectric constant of more than 300 is attained by IMS combined with SrRuO<sub>3</sub> electrodes
[Show abstract][Hide abstract] ABSTRACT: Low temperature (600°C) (Ba,Sr)TiO<sub>3</sub> (BST) capacitor
process integration (LTB) based on a SrRuO<sub>3</sub> (SRO) electrode
is proposed to achieve gigabit scaled and embedded DRAMs. The BST
crystallization temperature is successfully reduced by SRO, which has
the same perovskite structure as the BST film. Chemical Mechanical
Polishing (CMP) and O<sub>3</sub> water etching are developed for
storage node (SN) electrode and plate (PL) electrode patterning. A new
low temperature post anneal method is also proposed in order to reduce
oxygen vacancies at the top electrode-BST interface
[Show abstract][Hide abstract] ABSTRACT: All perovskite Capacitor (APEC) technology is proposed to achieve
(Ba,Sr)TiO<sub>3</sub> (BST) capacitor scaling toward 0.10 μm DRAM
generation. A conductive perovskite-oxide (polycrystalline SrRuO<sub>3
</sub> (SRO)) electrode is introduced as a bottom and a top electrode of
BST capacitor. Advantages of APEC technology are low leakage current and
less damage to hydrogen-annealing. A new BST-CVD tool with a good film
uniformity is also developed to realize a BST film thickness decrease.
Both APEC and the new BST-CVD tool are found to be a promising
technology for future BST capacitors scaling