[Show abstract][Hide abstract] ABSTRACT: Hot carrier injection (HCI) and negative bias temperature instability (NBTI) of fully depleted silicon-on-insulator (FD-SOI) CMOSFETs with thin-buried oxide (BOX) were investigated for the first time. A comparison with conventional bulk devices showed that no halo implant in this structure produces better reliability. The impact of back-biasing in thin-BOX FD-SOI devices on reliability is also reported.
[Show abstract][Hide abstract] ABSTRACT: We describe the observation of stimulated emissions by current injections into a silicon quantum well. The device consists of a free standing membrane with a distributed feedback resonant cavity fabricated by state-of-the-art silicon processes. The emission spectra have multimode structures peaked in the near-infrared region above the submilliampere threshold currents at room temperatures. Consequently, electronics and photonics should be able to be converged on chips by using silicon quantum well laser diodes.
No preview · Article · Dec 2009 · Applied Physics Letters
[Show abstract][Hide abstract] ABSTRACT: We have successfully demonstrated ldquosilicon on thin BOX (SOTB) 6T-SRAM with a 50-nm gate. By employing an ultra low-dose channel, this SOTB achieves small V<sub>th</sub> variability. As a result, the SOTB SRAM technology has been successfully developed with 0.142 V of static noise margin at V<sub>dd</sub>=0.6 V and V<sub>dd_min</sub> of 0.63 V because of its excellent V<sub>th</sub> variability characteristics. We also show that SOTB CMOS exhibits superior reliability and noise performance. These characteristics indicate robust properties for future industrial high performance and low power LSIs.
[Show abstract][Hide abstract] ABSTRACT: Ultra-low off current (Ioff < 1 pA/μm) “silicon on thin buried oxide (SOTB)” CMOSFETs were developed using 65-nm technology. The off current of SOTB CMOSFETs was studied and gate-induced drain leakage (GIDL) was adequately reduced by controlling the gate-overlap length. A back-gate bias in a SOTB scheme was demonstrated, and the inverter delay was compared with conventional low-standby-power bulk CMOSFETs. We show small variation in SOTB devices and estimate the standby leakage of a 1-M bit SRAM. The half threshold voltage standard deviation (σVth) of SOTB devices corresponds to a reduction in the standby leakage current of less than half. The ultra-low off current with a small variation also further reduces the standby leakage.
No preview · Article · Jul 2009 · Solid-State Electronics
[Show abstract][Hide abstract] ABSTRACT: We have observed net optical gain by current injections to ultra-thin Si embedded in a resonant optical cavity. The cavity consists of a dielectric waveguide fabricated by CMOS and MEMS process. The photoluminescence (PL) spectra show narrow resonances peaked at the designed wavelength, and the electroluminescence (EL) intensity increases super-linearly with currents. The comparisons with first principle calculations suggest that the optical gain is originated from intrinsic material properties of ultra-thin Si due to quantum confinements.
[Show abstract][Hide abstract] ABSTRACT: A ldquosilicon on thin BOXrdquo (SOTB) CMOS with a 50-nm single metal (FUSI) gate has been developed. By employing an intrinsic channel and a metal gate, this SOTB achieves the smallest V<sub>th</sub> variability ever reported. The measured Pelgrom coefficients of the SOTB were 1.8 and 1.5 for NMOS and PMOS, respectively, even in the case of relatively thick EOT of 1.9 nm. Both multi-V<sub>th</sub> control as well as suppression of short-channel effects were carried out simply by adjusting the impurity concentration beneath the BOX layer while keeping the channel almost intrinsic. Inverter delay and off-current were optimized by controlling gate-overlap length by means of a dual-layer offset spacer. It is shown that, within planar-type low-power CMOS devices, the SOTB is the most scalable because of its capability of multi-V<sub>th</sub> and excellent matching characteristics.
[Show abstract][Hide abstract] ABSTRACT: We confirmed enhanced electroluminescence by lateral carrier injections to quantum confined ultra-thin silicon. The optical intensity can be controlled by the back gate voltage, and the device operates as a light-emitting transistor.
[Show abstract][Hide abstract] ABSTRACT: The authors have demonstrated a new technique that enables defect-free SGE/ELO silicon layer fabrication by using in-situ HCl etch and H2 anneal planarization. This is significant, as now defect-free SEG/ELO silicon techniques can be used for the fabrication of low-power and high performance CMOSFETs technology with ultra-thin body/BOX layers
[Show abstract][Hide abstract] ABSTRACT: Transport properties were examined in monolayer and sub-monolayer films composed of Au nanoparticles covered with organic thiol ligands. In the monolayer film, the observed linear conductance scaled exponentially with the ligand chain length. On the other hand, in the sub-monolayer film, nonlinear current-voltage characteristics were observed as expected for one-dimensional meandering paths induced by structural defects.
[Show abstract][Hide abstract] ABSTRACT: We have elucidated the mechanism of the drive current enhancement in channel pMOSFETs on (100) substrate. In spite of the huge anisotropic effective mass, the long channel mobility (mueff) of is identical to that of , while it is enhanced when L and W are scaled. We found evidence that the origin is process induced stress, and the mueff enhancement is theoretically supported by the reduction of the average effective mass in a diffusive transport regime. We propose that a combination of channel and biaxial compressive stress is effective to enhance mueff
[Show abstract][Hide abstract] ABSTRACT: Defects in the supercritical thickness strained-Si layer grown on a fully relaxed SiGe buffer layer were investigated by atomic force microscopy (AFM) and transmission electron microscopy (TEM). The AFM observation of chemically etched surfaces showed that etch pits having a crosshatch pattern due to misfit dislocations decrease and segments and deep valley profiles increase with an increase in the strain energy of the Si. We found that the segment corresponds to an extended dislocation, of which a 30° partial is in the strained-Si layer and a 90° partial is in the SiGe layer, and the deep valley corresponds to a stacking fault found by a high-resolution TEM observation. A model of the generation of the stacking fault related to development of the misfit dislocation is also discussed here.
No preview · Article · Feb 2006 · Applied Physics Letters
[Show abstract][Hide abstract] ABSTRACT: We applied a strained-Si/relaxed-SiGe structure to LDMOSFETs in order to improve the power-added efficiency (PAE) of cellular handset RF power amplifier applications. Our LDMOSFETs were fabricated in a 70-nm-thick strained-Si/relaxed Si<sub>0.85</sub>Ge<sub>0.15</sub> structure. Despite of appearance of misfit dislocations, the thick strained-Si was essential for the high efficiency and low leakage. The self-heating effects on the power performance were estimated to be negligible by using a dynamic thermal simulation. The devices exhibited 46.7%-PAE at 27.5 dBm-P<sub>out</sub> for WCDMA a handset application, which was improved by 4.0 point over Si controls
[Show abstract][Hide abstract] ABSTRACT: Strained-silicon MOSFETs of both high breakdown voltage and low leakage current were fabricated by employing a thick strained-silicon layer. It is demonstrated that proper control of junction depth can drastically reduce leakage current although misfit dislocations exist at the strained-silicon/SiGe interface, and that breakdown voltage of strained-silicon MOSFETs kept the same high value as silicon MOSFETs even at elevated temperatures. RF performances such as f<sub>T</sub>, noise, and FR-power-amplifier efficiency were improved by this technology.
[Show abstract][Hide abstract] ABSTRACT: We demonstrate a new MOSFET on ultra-thin BOX that allows wide-range back-bias control in low-power and high-performance applications. The back gate is effective not only to increase the drive current by about 20% in active mode but also in reduce the off-current by an order of magnitude in stand-by mode. We have also demonstrated tunable-threshold-voltage technology for devices with metal gates and ion implantation for V<sub>th</sub> control. The target V<sub>th</sub> for low-power applications was achieved by using ion implantation for V<sub>th</sub> control. We propose a 6-transistor SRAM memory cell in which we obtain even more benefit from the new device structure by adding a feedback mechanism. A proposed 6-Tr SRAM memory cell is shown to dramatically improve SNM characteristics at the 65-nm technology nodes, and this effect will also apply at finer nodes.
[Show abstract][Hide abstract] ABSTRACT: Silicon semiconductor (MOSFET: metal-oxide semiconductor field-effect transistor) dimensions are approaching the nanometer scale. The gate electrode size has already been reduced to 50 nm or less for the most advanced 90-nm technology nodes, and for the 65-nm nodes the size is expected to be 25 nm. A new guideline to replace the scaling rule is needed, and making use of the strain effect or 3D device structure design have attracted attention as a means of meeting that need. Technology that makes use of material strain requires highly accurate evaluation technology for strain and control of defects possibly caused by the strain. Substrate etching is a very important process in achieving a 3D MOSFET. Nanometer-scale precision, removal of processed surface damage and evaluation technology for that are essential.
[Show abstract][Hide abstract] ABSTRACT: We have developed the new "Yin-Yang" feedback technology for SRAM cells. This technology is applied to six-transistor cells and four-transistor cells, which are composed of transistors with the new D2G-SOI structure. At the 65-nm process node, these cells can operate at 0.7 V in mass-produced LSIs under real usage conditions. Max operating speeds are 300 MHz for the six-transistor and 200 MHz for the four-transistor cell. Leakage current of the four-transistor cell is about 1/1000 that of a conventional four-transistor cell. These cells provide a SRAM menu that allows us to optimally balance the requirements of various types of SRAM in low-power LSIs.
[Show abstract][Hide abstract] ABSTRACT: We examined reduced mobility for MISFETs with high-κ gate dielectrics, which cannot be explained just by one scattering mechanism. We developed a comprehensive mobility model, in which various possible scattering sources, including fixed charges, roughness, and phase separation, are unified to account for the reduced mobility.
[Show abstract][Hide abstract] ABSTRACT: Semiconductor manufacturers' particular emphasis is on providing LSI (large-scale integration) devices as best solutions in its lineup of microcomputer-based specialty products. This will involve not only performance and functionality, but an equal emphasis on holding down costs, achieving exceptional reliability, and minimizing time to market in developing new products. Supporting these efforts are semiconductor device technology and manufacturing equipment built by Hitachi Group, common technologies developed through national projects and consortiums, and high-reliability high-yield manufacturing technologies. By combining a silicon technology platform based on these manufacturing technologies and core technology-based devices, the Hitachi Group contributes to produce a wide range of specialty products and responds quickly to new user demands.
[Show abstract][Hide abstract] ABSTRACT: A SiN dielectric with oxygen-enriched interface (OI-SiN) was applied as an interfacial layer of an Al<sub>2</sub>O<sub>3</sub> stack. The OI-SiN interface, where the nitrogen profile is controlled and the fixed charge is suppressed, can solve critical issues for high-κ dielectrics; impurity penetration through conventional processes, and reduced mobility due to Coulomb scattering. Thus, the drivability with low-leakage current is ensured. We show a scaling strategy to integrate the OI-SiN/Al<sub>2</sub>O<sub>3</sub> stack which is suitable for low-power applications.