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ABSTRACT: The CALICE collaboration is undertaking a major R&D programme into calorimetry for the International Linear Collider (ILC). The programme includes the development and test of electromagnetic calorimeter (ECAL) prototypes. The ECAL is built by interleaving Tungsten layers with very thin, multi layer PCBs integrating the Silicon sensors, the Very Front End chips, and electrical infrastructure. These instrumentation slabs are assembled from multiple PCB panels, requiring reliable, high quality panel interconnects. In this paper, the focus is on two aspects of the distribution of high-speed signals towards many chips across multiple panels. Firstly, the distribution of high-speed (clock) signals from a single source towards many chips over large distances is discussed, followed by a presentation on the application of various interconnect technologies for non-invasive joining of very thin multi layer PCBs. The proposed interconnects are studied, and simulation and measurement results on signal transmission properties are presented. Results of studies using a realistic, full-length slab prototype containing FPGAs emulating VFE chips are discussed. The paper is concluded with recommendations regarding the panel interconnect properties, and the distribution of high speed signals towards many chips over metre-scale distances. The work described above is part of the UK programme to develop a data acquisition system for CALICE.
University of Cambridge
Cambridge, England, United Kingdom
- Department of Physics: Cavendish Laboratory