K. S. Yew

Nanyang Technological University, Tumasik, Singapore

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Publications (13)22.28 Total impact

  • Kwang Sing Yew · Diing Shenp Ang · Lei Jun Tang · Jisheng Pan
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    ABSTRACT: The authors show that the TiN/HfO2/SiOx gate stack, formed via multistep deposition cum two-step anneal [comprising a room-temperature ultraviolet ozone (RTUVO) anneal and a subsequent rapid thermal anneal (RTA) at 420 °C], exhibits more superior electrical characteristics as compared to the gate stacks formed via multistep deposition cum single-step anneal (either RTUVO anneal or 420 °C RTA). The former exhibits more than an order of magnitude smaller gate current density, a 14-fold increase in the time-to-breakdown, and reduced positive oxide trapped charge as compared to the latter. The enhanced performance and reliability are attributed to the improved formation of Hf-O bonds in HfO2, resulting from the efficient incorporation of oxygen atoms facilitated by the thermal activation of the absorbed ozone. The findings provide insights into the improvement mechanism by the two-step anneal method for high-k last integration scheme.
    No preview · Article · Jan 2016
  • D. S. Ang · T. Kawashima · Y. Zhou · K. S. Yew · M. K. Bera · H. Zhang

    No preview · Article · Oct 2015 · ECS Transactions
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    ABSTRACT: Nanoscale conducting filament, which forms the basis of the HfO2 resistive memory, is shown to exhibit a “negative photoconductivity” behavior, in that, electrical conduction through it can be disrupted upon white-light illumination. This behavior should be contrasted against the positive photoconductivity behavior commonly exhibited by oxides or perovskites having narrower bandgaps. The negative photoconductivity effect may be explained in terms of a photon-induced excitation of surrounding oxygen ions, which leads to migration and subsequent recombination with vacancies in the conducting filament. The finding suggests possible electrical-cum-optical applications for HfO2-based devices, whose functionality is limited to-date by electrical stimulation.
    No preview · Article · Aug 2015 · Applied Physics Letters
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    ABSTRACT: From conductive-atomic-force-microscope probe measurement, we show that electrical conduction through a nanoscale percolation path in the MOSFET gate oxide can be disrupted, either completely or partially, by white-light illumination. This phenomenon is consistently observed in the SiO2 and HfO2 gate-oxide materials, and thus is believed to have originated from a common mechanism—light-stimulated oxygen migration and recombination with vacancy sites that constitute the percolation path. The finding points to the prospect of reliability rejuvenation by the light-assisted restoration of postelectrical-breakdown gate oxides, as well as light-enabled memory operation based on logic MOSFET devices.
    No preview · Article · Aug 2015 · IEEE Electron Device Letters
  • H. Z. Zhang · D. S. Ang · C. J. Gu · K. S. Yew · X. P. Wang · G. Q. Lo
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    ABSTRACT: The role of the bottom interfacial layer (IL) in enabling stable complementary resistive switching (CRS) in the TiN/HfOx/IL/TiN resistive memory device is revealed. Stable CRS is obtained for the TiN/HfOx/IL/TiN device, where a bottom IL comprising Hf and Ti sub-oxides resulted from the oxidation of TiN during the initial stages of atomic-layer deposition of HfOx layer. In the TiN/HfOx/Pt device, where formation of the bottom IL is suppressed by the inert Pt metal, no CRS is observed. Oxygen-ion exchange between IL and the conductive path in HfOx layer is proposed to have caused the complementary bipolar switching behavior observed in the TiN/HfOx/IL/TiN device.
    No preview · Article · Dec 2014 · Applied Physics Letters
  • K. S. Yew · D. S. Ang · L. J. Tang
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    ABSTRACT: We show that multistep deposition cum two-step annealing, comprising an ultraviolet ozone (UVO) anneal followed by a low-temperature rapid thermal anneal (RTA), can significantly improve the performance and reliability of a 7.5-angstrom-equivalent-oxide-thickness (EOT) HfO2/TiN gate stack, comprising a 25-angstrom HfO2 on similar to 3 angstrom SiOx, i.e., prepared from direct HfO2 deposition onto an HF-last Si surface. The method yields approximately two orders of magnitude reduction in gate current density and approximately an order of magnitude longer time to breakdown, as compared with the as-deposited gate stack. The observed improvements may be attributed to the "repair" of oxygen-vacancy defects at the HfO2/Si interface and in the HfO2 bulk by the absorbed ozone, through thermal activation provided by the RTA step. The findings provide a promising means for realizing low-leakage and reliable sub-1-nm EOT HfO2/TiN stacks for high-k last integration.
    No preview · Article · Feb 2013 · IEEE Electron Device Letters
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    ABSTRACT: The quality of germanium (Ge) epitaxial film grown directly on silicon (Si) substrate is investigated based on the electrical properties of a metal-oxide-semiconductor capacitor (MOSCAP). Different thermal cycling temperatures are used in this study to investigate the effect of temperature on the Ge film quality. Prior to high-k dielectric deposition, various surface treatments are applied on the Ge film to determine the leakage current density using scanning tunneling microscopy. The interface trap density (D-it) and leakage current obtained from the C-V and I-V measurements on the MOSCAP, as well as the threading dislocation density (TDD), show a linear relationship with the thermal cycling temperature. It is found that the Ge epitaxial film that undergoes the highest thermal cycling temperature of 825 degrees C and surface treatment in ultraviolet ozone, followed by germanium oxynitride (GeOxNy) formation, demonstrates the lowest leakage current of similar to 2.3 x 10(-8) A/cm(2) (at -2 V), D-it similar to 3.5 x 10(11) cm(-2)/V, and TDD < 10(7) cm(-2).
    No preview · Article · Jan 2013 · IEEE Transactions on Electron Devices
  • K. S. Yew · D. S. Ang
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    ABSTRACT: The TiN/HfZrO/SiOx gate stack formed via multi-step deposition cum room-temperature ultraviolet-ozone (UVO) anneal was examined using scanning tunneling microscopy and pulse capacitance-voltage measurement, and the results were compared with those of the as-deposited (as-dep) and rapid-thermal-annealed (RTA) samples. Evidence shows that a large part of the improvement seen in the multistep-deposited cum UVO-annealed sample, relative to the RTA sample, is a direct consequence of suppressed crystallization of the HfZrO and, hence, a reduction in the density of grain-boundary-related defects. Compared with the as-dep sample, the observed improvement due to UVO annealing is marginal, although further improvement, ascribed to the elimination of oxygen-vacancy defects, may be achieved by either increasing the UVO anneal time after each deposition step or increasing the number of deposition steps. This makes multistep deposition and UVO annealing viable for further enhancing the robustness of the high-k gate dielectric in a gate-last process.
    No preview · Article · Aug 2012 · IEEE Transactions on Electron Devices
  • K. S. Yew · D. S. Ang · G. Bersuker
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    ABSTRACT: We provide new insights, via nanoscale TDDB testing, into the bimodal Weibull failure distribution obtained from area scaling of high-kappa (HK) gate stack. Time-to-breakdown (BD) statistics for grain boundary (GB) and grain in a polycrystalline HK gate stack are obtained individually from localized constant voltage stressing via a scanning tunneling microscope. In spite of an initial difference in the preexisting defect density, no apparent difference in the Weibull slope is observed for the two sets of BD statistics. The bimodal Weibull distribution is shown to be a combined effect: 1) The steep Weibull slope of the lower percentile, arising from large-area devices, is related to BD at GBs, and 2) the upper percentile, arising from small-area devices, is mostly related to grain BDs. In this case, the Weibull slope is reduced by a small fraction of these devices exhibiting early failures due to GB BDs. We show directly that structural defects in an HK dielectric, particularly GBs, play an important role on its BD distribution.
    No preview · Article · Feb 2012 · IEEE Electron Device Letters
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    ABSTRACT: Electrical and reliability characteristics of the HfSiO x high-permittivity (high-k) gate dielectric formed via a single-step and a multi-step deposition-cum-annealing method are examined via ultrahigh-vacuum scanning tunneling microscopy (STM). Unlike the single-step high-k, which exhibits coarse granular features indicating that transformation to a polycrystalline phase has occurred, the multi-step high-k of equivalent physical thickness is observed to retain the nanocrystalline STM characteristics following a high temperature (∼1000°C) anneal. After the localized electrical stress using the STM probe, the multi-step high-k film shows better leakage current uniformity and higher breakdown voltage comparing to those of the single-step film, consistent with the results of the metal-oxide-semiconductor capacitor measurements. The improvements may be ascribed to a partially suppressed formation of the grain boundaries in thin films constituting the multi-step dielectric, which reduces the grain-boundary related low-resistance paths through the dielectric. The results indicate that the multi-step deposition process can improve electrical characteristics of the high-k gate dielectrics.
    No preview · Article · Sep 2011
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    ABSTRACT: In this brief, high-κ HfZrO (via atomic layer deposition) fabricated by a novel multideposition multiroom-temperature annealing (MDMA) technique in ultraviolet-ozone (UVO) ambient is systematically investigated by both electrical and physical characterization and is integrated with a TiN metal gate in a gate-last process. Compared with the conventional rapid-thermal-annealed sample, it is found that the device annealed via MDMA in UVO demonstrates the following: 1) more than one order of leakage current reduction at 25°C and 125°C without an equivalent oxide thickness penalty; 2) less susceptibility to stress-induced degradation; and 3) improved time-dependent dielectric-breakdown lifetime. Grain boundary suppression and healing of oxygen vacancies are believed to be responsible for the improvement, as evidenced by scanning tunneling microscopy and X-ray photoelectron spectroscopy analysis.
    No preview · Article · Aug 2011 · IEEE Transactions on Electron Devices
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    ABSTRACT: A mechanism of degradation and breakdown in high-k/metal gate transistors was investigated. Based on the electrical test, physical analysis, and modeling results, we propose that the breakdown path formation/evolution in the interfacial SiO<sub>2</sub> layer is associated with the growth of an oxygen-deficient filament facilitated by the grain boundaries of the overlaying high-k film. The model allows reproducing SILC temperature dependency and its exponential increase from the fresh through soft and progressive breakdown phases.
    No preview · Conference Paper · Jun 2010
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    ABSTRACT: ALD HfZrO high-K fabricated by novel multi deposition multi annealing (MDMA) technique at room temperature in Ultraviolet-Ozone (UVO) ambient is systematically investigated for the first time via both physical and electrical characterization. As compared to the reference gate stack treated by conventional rapid thermal annealing (RTA) @ 600°C for 30 s (with PVD TiN electrode), the devices receiving MDMA in UVO demonstrates: 1) more than one order of magnitude leakage reduction without EOT penalty at both room temperature and an elevated temperature of 125°C; 2) much improved stress induced degradation in term of leakage increase and flat band voltage shift (both room temperature and 125°C); 3) enhanced dielectrics break-down strength and time-dependent-dielectric-breakdown (TDDB) life time. The improvement strongly correlates with the cycle number of deposition and annealing (D&A, while keeping the total annealing time and total dielectrics thickness as the same). Scanning tunneling microscopy (STM) and X-ray photoelectron spectroscopy (XPS) analysis suggest both oxygen vacancies (Vo) and grain boundaries suppression in the MDMA treated samples are likely responsible for the device improvement. The novel room temperature UVO annealing is promising for the gate stack technology in a gate last integration scheme.
    No preview · Article · Jan 2010 · Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International