G. M. Cohen

IBM, Armonk, New York, United States

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Publications (38)32.42 Total impact

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    ABSTRACT: For Gate-All-Around (GAA) MOSFETs the nanowires are suspended between source and drain anchors allowing conformal deposition of the gate around (i.e., GAASiNW) the silicon nanowire channel. 3DSEM measurement show that silicon wires tend to buckle between the source and drain anchors as function of their diameter and length. This phenomenon can impact device performance and therefore needs to be characterized. Resent metrology research performed on Silicon nanowires fabricated over a Boron Nitride (BN) layer demonstrated that Silicon nanowires spatial orientation is influenced by local electrostatic charge induced by the SEM electron beam irradiation. The scanning electron beam leads to charging of the floating conductive silicon wires and dielectric BN layer. Difference in charging mechanisms of the two materials lead to the formation of Coulomb forces acting between the wires and the BN layer. We were able to change the spatial orientation of Silicon nanowires by modifying scanning conditions which effectively controls the amount of charging induced by the SEM. Strong charging, which corresponds to high dose leads to change of silicon wires spatial orientation, they appear straight in SEM top view and tilt image planes. Reducing charging by the means of scan rate increase or lower number of scanned frames saves the silicon wires buckled in their natural state.
    No preview · Article · Jan 2015 · Proceedings of SPIE - The International Society for Optical Engineering
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    ABSTRACT: Processing and synthesis of purified nanomaterials of diverse composition, size, and properties is an evolving process. Studies have demonstrated that some nanomaterials have potential toxic effects and have led to toxicity research focusing on nanotoxicology. About two million workers will be employed in the field of nanotechnology over the next 10 years. The unknown effects of nanomaterials create a need for research and development of techniques to identify possible toxicity. Through a cooperative effort between National Institute for Occupational Safety and Health and IBM to address possible occupational exposures, silicon-based nanowires (SiNWs) were obtained for our study. These SiNWs are anisotropic filamentary crystals of silicon, synthesized by the vapor-liquid-solid method and used in bio-sensors, gas sensors, and field effect transistors. Reactive oxygen species (ROS) can be generated when organisms are exposed to a material causing cellular responses, such as lipid peroxidation, H2O2 production, and DNA damage. SiNWs were assessed using three different in vitro environments (H2O2, RAW 264.7 cells, and rat alveolar macrophages) for ROS generation and possible toxicity identification. We used electron spin resonance, analysis of lipid peroxidation, measurement of H2O2 production, and the comet assay to assess generation of ROS from SiNW and define possible mechanisms. Our results demonstrate that SiNWs do not appear to be significant generators of free radicals.
    Full-text · Article · Nov 2014 · Environmental Health Insights
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    ABSTRACT: In this work, we report a new fabrication method of Si nanowires that enables an accurate control of the suspension gap underneath the Si wire. It is achieved by using SOI wafers with an embedded boron nitride (BN) etch-stop layer. Physical characterization of the Si wires was performed with a 3D-CDSEM, measurement results are compared with the process of record where conventional SOI wafers are used. Metrology measurements provide new insights on the effect of SEM induced charge in altering the buckling orientation of imaged Si wires.
    No preview · Conference Paper · May 2014
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    ABSTRACT: In an ongoing study of the physical characterization of Gate-All-Around Silicon Nano Wires (GAASiNW), we found that the thin, suspended wires are prone to buckling as a function of their length and diameter. This buckling takes place between the fixed source and drain regions of the suspended wire, and can affect the device performance and therefore must be studied and controlled. For cylindrical SiNW, theory predicts that buckling has no directional preference. However, 3D CDSEM measurement results indicated that cylindrical wires prefer to buckle towards the wafer. To validate these results and to determine if the electron beam or charging is affecting our observations, we used 3D-AFM measurements to evaluate the buckling. To assure that the CDSEM and 3D-AFM measure the exact same locations, we developed a design based recipe generation approach to match the 3D-AFM and CDSEM coordinate systems. Measuring the exact same sites enables us to compare results and use 3D-AFM data to optimize CDSEM models. In this paper we will present a hybrid metrology approach to the characterization of GAASiNW for sub-nanometer variations, validating experimental results, and proposing methods to improve metrology capabilities.
    No preview · Conference Paper · Apr 2014
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    ABSTRACT: We present results from gate-all-around (GAA) silicon nanowire (SiNW) MOSFETs fabricated using a process flow capable of achieving a nanowire pitch of 30 nm and a scaled gate pitch of 60 nm. We demonstrate for the first time that GAA SiNW devices can be integrated to density targets commensurate with CMOS scaling needs of the 10 nm node and beyond. In addition, this work achieves the highest performance for GAA SiNW NFETs at a gate pitch below 100 nm.
    No preview · Conference Paper · Dec 2013
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    ABSTRACT: Imaging of suspended silicon nanonwires (SiNW) by SEM reveals that some of the SiNW are buckled. Buckling can impact device performance and it is therefore important to characterize this phenomenon. Measuring the buckling of suspended silicon nanowires (SiNW) poses significant challenges: (1) Small dimensions - SiNW are made with diameters ranging from about 3 to 10 nm and the buckling is of a similar scale. (2) Accurate height measurements – buckling is a three dimensional phenomena. To meet these challenges a new height map reconstruction technique was introduced, using the CDSEM side detectors signal. Measuring pixel by pixel position in X, Y and Z (height) dimensions, we can obtain the buckling vector gradient along the wire in three dimensions. In this paper we present: (1) A description of the height map reconstruction technique used. (2) Three dimensional characterization of SiNW: (a) SiNW buckling measurements (b) Characterization of buckling as a function of the SiNW length and width.
    No preview · Conference Paper · Apr 2013
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    ABSTRACT: Silicon nanowires (Si NWs) are being manufactured for use as sensors and transistors for circuit applications. The goal was to assess pulmonary toxicity and fate of Si NW using an in vivo experimental model. Male Sprague-Dawley rats were intratracheally instilled with 10, 25, 50, 100, or 250 μg of Si NW (~20–30 nm diameter; ~2–15 μm length). Lung damage and the pulmonary distribution and clearance of Si NW were assessed at 1, 3, 7, 28, and 91 days after-treatment. Si NW treatment resulted in dose-dependent increases in lung injury and inflammation that resolved over time. At day 91 after treatment with the highest doses, lung collagen was increased. Approximately 70% of deposited Si NW was cleared by 28 days with most of the Si NW localized exclusively in macrophages. In conclusion, Si NW induced transient lung toxicity which may be associated with an early rapid particle clearance; however, persistence of Si NW over time related to dose or wire length may lead to increased collagen deposition in the lung.
    Preview · Article · May 2012 · Journal of Nanomaterials
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    ABSTRACT: In this paper we present physical characteristics of Silicon Nano Wires (SiNW) fabrication processes, in line SEM metrology measurements, and a new methodology to calibrate and correct in line roughness measurements, improving measurement accuracy. Silicon Nano Wires (SiNW) with widths of 5 - 25 nm were characterized. Hydrogen annealing was shown as a useful method for the fabrication of smooth suspended SiNW that are used to build gate-all-around MOSFETs [1]. Wires that were annealed in H2 exhibit surface roughness below 1 nm along the full length of the 100 nm long suspended wires. Different smoothing processes yield SiNWs with edge roughness values in the sub nanometer range. Such small differences in roughness values, provide an interesting opportunity to evaluate sensitivity of the SEM metrology algorithms and measurement accuracy. A simulation program modeling SEM images including small features was developed, taking into account the main factors that affect the SEM signal formation. Synthetic (simulated) images of SiNW in a range of 5 - 25 nm and roughness of 0 - 1 nm were produced. Using synthetic images with added Line Edge Roughness (LER), we characterized the performance and sensitivity of LER algorithms and metrics. Fabricated SiNW that received various smoothing and thinning treatments were measured with a CD-SEM. Results were compared to calibrate and validate the experimental CD-SEM results.
    No preview · Article · Mar 2012 · Proceedings of SPIE - The International Society for Optical Engineering
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    ABSTRACT: Anneal in reduced pressure hydrogen ambient is known to induce morphological changes in silicon microstructures via markedly increased surface self-diffusivity on exposed silicon surfaces. Here, we investigate the capillary instability of silicon nanostructures under hydrogen anneal. We demonstrate that a surface diffusion mask can significantly improve stability by isolating vulnerable segments from large mass reservoirs. In addition, we find that Plateau-Rayleigh instability shows strong crystallographic dependence, which is explained by the surface energy anisotropy of silicon. We observe that nanowires are the least stable when their axial orientation corresponds to 〈100〉 and are increasingly stable for 〈111〉, 〈112〉, and 〈110〉.
    No preview · Article · Mar 2012 · Applied Physics Letters
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    ABSTRACT: Room-temperature carrier transport in Si nanowire (NW) MOSFETs with gate lengths and diameters down to 25 and 8 nm, respectively, is analyzed. It is shown that in Si NWs, holes exhibit channel injection and thermal velocities, as high as the highest obtained for uniaxially strained planar Si-channel electrons, likely due to combination of strain and confinement.
    Full-text · Conference Paper · Jan 2012
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    ABSTRACT: The ability to prepare multiple cross-section transmission electron microscope (XTEM) samples from one XTEM sample of specific sub-10 nm features was demonstrated. Sub-10 nm diameter Si nanowire (NW) devices were initially cross-sectioned using a dual-beam focused ion beam system in a direction running parallel to the device channel. From this XTEM sample, both low- and high-resolution transmission electron microscope (TEM) images were obtained from six separate, specific site Si NW devices. The XTEM sample was then re-sectioned in four separate locations in a direction perpendicular to the device channel: 90° from the original XTEM sample direction. Three of the four XTEM samples were successfully sectioned in the gate region of the device. From these three samples, low- and high-resolution TEM images of the Si NW were taken and measurements of the NW diameters were obtained. This technique demonstrated the ability to obtain high-resolution TEM images in directions 90° from one another of multiple, specific sub-10 nm features that were spaced 1.1 μm apart.
    No preview · Article · Nov 2011 · Microscopy and Microanalysis
  • G. M. Cohen · P. M. Mooney · J.O. Chu
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    ABSTRACT: We show that SiGe grown on free-standing silicon is elastically relaxed. The free-standing Si structure consists of a ∼30 nm-thick, 5 μm-square silicon slab supported by a SiO2 pedestal at a single contact point at the center of the square (the cross-section resembles a mushroom). A matrix of free-standing structures was made by patterning a bonded silicon-on-insulator (SOI) wafer and undercutting the SiO2 to form the pedestal. Un-patterned areas of the SOI wafer and the exposed bulk Si substrate were included as reference regions. A UHVCVD Si0.8Ge 0.2 film, about 200 nm-thick, was grown epitaxially on both sides of the free-standing silicon and the surrounding exposed bulk Si. The SiGe was also grown on the un-patterned SOI and bulk substrate control areas. The SiGe film grown on both SOI and bulk silicon was found to be fully strained. In contrast, the SiGe layer grown on free-standing silicon is ∼89% strain-relaxed, and the free-standing silicon film was measured to be under tensile strain. Since the same lattice mismatch was found between the SiGe layer and the Si on the free-standing silicon and on the SOI and bulk Si control regions, we conclude that the strain relaxation of the SiGe film on freestanding Si is elastic with the strain accommodated entirely by the free-standing silicon film under tensile strain. This was further confirmed by AFM measurements. The SiGe film on the control regions showed a very smooth SiGe surface with only a few surface steps originating from misfit dislocations at the SiGe/Si interface. No surface steps from misfit dislocations were observed on the surface of the SiGe film on free-standing Si. These results show that free-standing silicon serves as an ideal compliant substrate for SiGe.
    No preview · Article · Jan 2011 · MRS Online Proceeding Library
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    ABSTRACT: We discuss a modified self-aligned silicide (salicide) process that uses a silicon cap to reduce the substrate silicon consumption by 50% as compared with a conventional salicide process. We have used a metal-silicon mixture to form the metal-rich phase reliably in the first anneal. After etching the unreacted mixture we deposit a silicon cap. This forces the metal to react with the silicon cap as well as with the substrate during the second anneal, thus minimizing silicon consumption from the substrate. The unreacted portion of the silicon cap is selectively etched, leaving a structure with a raised source and drain. We expect this process to be useful for forming silicide on shallow junctions and thin SOI films, where silicon consumption is constrained.
    No preview · Article · Jan 2011 · MRS Online Proceeding Library
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    ABSTRACT: Experimental data from undoped-body gate-all-around (GAA) silicon nanowire (NW) MOSFETs with different sizes demonstrate the universality of short-channel effects as a function of L <sub>EFF</sub>/λ, where L <sub>EFF</sub> is the effective channel length and λ is the electrostatic scaling length. Data from undoped-body single-gate extremely thin SOI (ETSOI) devices additionally show that the universality of short-channel effects is valid for any undoped-body fully depleted SOI MOSFET. Our data indicate that L <sub>EFF</sub> of undoped GAA NW MOSFETs can be scaled down by ~2.5 times compared with undoped single-gate ETSOI MOSFETs while maintaining equivalent short-channel control.
    Full-text · Article · Oct 2010 · IEEE Electron Device Letters
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    ABSTRACT: We demonstrate undoped-body, gate-all-around (GAA) Si nanowire (NW) MOSFETs with excellent electrostatic scaling. These NW devices, with a TaN/Hf-based gate stack, have high drive-current performance with NFET/PFET I<sub>DSAT</sub> = 825/950 μA/μm (circumference-normalized) or 2592/2985 μA/μm (diameter-normalized) at supply voltage V<sub>DD</sub> = 1 V and off-current I<sub>OFF</sub> = 15 nA/μm. Superior NW uniformity is obtained through the use of a combined hydrogen annealing and oxidation process. Clear scaling of short-channel effects versus NW size is observed. Additionally, we observe a divergence of the nanowire capacitance from the planar limit, as expected, as well as enhanced device self-heating for smaller diameter nanowires. We have also applied this method to making functional 25-stage ring oscillator circuits.
    Full-text · Conference Paper · Jul 2010
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    ABSTRACT: We demonstrate the world's first top-down CMOS ring oscillators (ROs) fabricated with gate-all-around (GAA) silicon nanowire (NW) FETs having diameters as small as 3 nm. NW capacitance shows size dependence in good agreement with that of a cylindrical capacitor. AC characterization shows enhanced self-heating below 5 nm.
    Full-text · Conference Paper · Jul 2010

  • No preview · Article · Jul 2010 · Microscopy and Microanalysis
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    ABSTRACT: Gate-all-around p-i-n silicon nanowires (NW) diodes with effective nanowire diameter from 15 nm down to 4 nm (±1.3 nm) were fabricated to enable interface state density (Nιι) measurements using the charge pumping (CP) method. The Nη of the NWs was also measured by the conductance method and was in good agreement with the CP method. The linear relation between the CP current and the pulse frequency was not maintained in the smallest diameter NWs. The dependency on the pulse rise and fall times was also investigated and is correlated to the lifetime of the traps. The impact of the cylindrical geometry on the measured CP current is discussed.
    Full-text · Article · Jun 2010

  • No preview · Conference Paper · May 2010
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    ABSTRACT: We demonstrate undoped-body, gate-all-around (GAA) Si nanowire (NW) MOSFETs with excellent electrostatic scaling. These NW devices, with a TaN/Hf-based gate stack, have high drive-current performance with NFET/PFET I<sub>DSAT</sub> = 825/950 ¿A/¿m (circumference-normalized) or 2592/2985 ¿A/¿m (diameter-normalized) at supply voltage V<sub>DD</sub> = 1 V and off-current I<sub>OFF</sub> = 15 nA/¿m. Superior NW uniformity is obtained through the use of a combined hydrogen annealing and oxidation process. Clear scaling of short-channel effects versus NW size is observed.
    Full-text · Conference Paper · Jan 2010