R.W. Dutton

Stanford University, Stanford, California, United States

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Publications (221)142.06 Total impact

  • Source
    L.M. Hillkirk · Jung-Hoon Chun · R.W. Dutton
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    ABSTRACT: Transient device simulations reproducing conditions similar to Electro-Static Discharge (ESD) conditions have been performed for the entire safe operating area (SOA) of a 0.13 μm technology, ground-gated N-channel Metal-Oxide-Semiconductor (ggNMOS) transistor up to 2<sup>nd</sup> breakdown, using a set of macroscopic physical models related to previous studies implemented in MEDICI. The simulations results indicate the potential influence of a source-end mechanism of destruction, in addition to the previously reported drain-end avalanche generation of electron-hole pairs and subsequent thermal runaway in the proximity of the carriers generation spot as a result of the large carrier density. Under dynamic conditions and with non-zero contact resistance, thermal runway is also observed on the source-side of the device indicating that, for values of the contact resistance on the order of 5.4e<sup>-6</sup> Ohms-cm<sup>2</sup>, substantial damage can occur at the source end. The simulation results are in qualitative agreement with experimental results where it is observed that, after electrical and subsequent thermal runaway, damage is localized not only at the drain region but also at the source region of the device. Thus, the ESD related destruction of a 0.13 μm gate ggNMOS may not be the result of a single destruction mechanism, but the consequence of coupled events, depending on the design characteristics of a particular device.
    Full-text · Conference Paper · Oct 2003
  • Source
    Tae-young Oh · C. Jungemann · R.W. Dutton
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    ABSTRACT: A noise model for MOSFETs based on analytical microscopic noise sources has been developed and noise simulations based on the hydrodynamic model have been performed. The drain and gate excess noise parameters and correlation coefficient are extracted and the reasons for noise parameter dependence on the channel length are explained.
    Preview · Conference Paper · Oct 2003
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    ABSTRACT: Degraded junction leakage current in scaled MOSFETs due to enhanced band-to-band tunneling (i.e. local Zener effect) is characterized based on a modified band-to-band tunneling model. To suppress the severe drain leakage current in the presence of high-dose halo implants, the impact of implant conditions on drain leakage current is estimated based on implant induced damage (point defect) profiles.
    Full-text · Conference Paper · Oct 2003
  • Source
    Eric Pop · R.W. Dutton · Kenneth E. Goodson
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    ABSTRACT: As current device technologies advance into the sub-continuum regime, they operate at length scales on the order of the electron and phonon mean free path. The ballistic conditions lead to strong non-equilibrium at nanometer length scales. The electron-phonon interaction is not energetically or spatially uniform and the generated phonons have widely varying contributions to heat transport. This work examines the microscopic details of Joule heating in bulk silicon with Monte Carlo simulations including acoustic and optical phonon dispersion. The approach provides an engineering tool for electro-thermal analysis of future nano-devices.
    Full-text · Conference Paper · Oct 2003
  • Jaejune Jang · Zhiping Yu · R.W. Dutton
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    ABSTRACT: An accurate method to extract a small signal equivalent circuit model of RF silicon MOSFETs is presented. Analytical calculations are used for each intrinsic parameter and accuracy is within 1% for the entire operational region. 2D physical device simulation is used to analyze this methodology. A simple non-quasi static (NQS) model is reported, which offers good accuracy needed for circuit simulation, including a simple network representing the coupling between source and drain. Accurate extraction methods for extrinsic parameters have been also developed. The compact model and its parameter extraction are verified on Si-MOSFETs through S-parameter measurements.
    No preview · Conference Paper · Jul 2003
  • Source
    Hai Lan · Zhiping Yu · R.W. Dutton
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    ABSTRACT: A simple, efficient CAD-oriented equivalent circuit modeling approach of frequency-dependent behavior of substrate noise coupling is presented. It is shown that the substrate exhibits significant frequency-dependent characteristics for high frequency applications using epitaxial layers on a highly doped substrate. Using the proposed modeling approach, circuit topographies consisting of only ideal lumped circuit elements can be synthesized to accurately represent the frequency response using y-parameters. The proposed model is well-suited for use in standard circuit simulators. The extracted model is shown to be in good agreement with rigorous 3D device simulation results.
    Preview · Conference Paper · Apr 2003
  • Zhiping Yu · D. W. Yergeau · R.W. Dutton
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    ABSTRACT: An accurate and general algorithm for evaluating vector quantities, such as electric field, at the nodes in a finite volume discretization is presented. The algorithm is based on the integral form of Poisson's and the carrier continuity equations. Application to the analysis of sub-50nm MOSFETs with quantum mechanical (QM) effects is demonstrated. Other applications include the coupled electrothermal simulation (Joule heat) and modeling of impact ionization.
    No preview · Conference Paper · Feb 2003
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    ABSTRACT: A physically based model has been formulated to represent temperature-dependent specific contact resistance. The new model can generate silicided contact resistance values at high temperatures and is capable of predicting high current behavior of silicided deep submicron devices. Implications for failure analysis of advanced silicided devices are also considered. Using the model, it has been demonstrated how current localization is affected by increased temperature, which is critical for predicting ESD reliability.
    Full-text · Conference Paper · Jan 2003
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    Eric Pop · Robert Dutton · Kenneth Goodson
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    ABSTRACT: This paper explores the effect of confined dimensions and complicated geometries on the self-heating of ultra-thin body SOI and FinFET devices. A compact thermal model is introduced, incorporating the most advanced understanding of nanoscale heat conduction available. Novel device scaling is analyzed from a thermal point of view. We show device temperatures are very sensitive to the choice of drain and channel extension dimensions, and suggest a parameter design space which can help alleviate thermal problems. ITRS power guidelines below the 25 nm technology node should be revised if isothermal scaling of thin-body devices is desired.
    Full-text · Article · Jan 2003 · Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International
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    ABSTRACT: Using a scaling length (λ) analysis, the short-channel effects of bulk MOSFETs with super-steep retrograded channels (SSR), fully-depleted SOI, and double-gate structures are investigated. It is found that the minimum channel length should be greater than 5λ and the depletion thickness of the SSR should be less than 30 nm in order to be applicable to 70 nm CMOS technology
    Full-text · Article · Oct 2002 · Electronics Letters
  • Source
    C. Ito · K. Banerjee · R.W. Dutton
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    ABSTRACT: Electrostatic discharge (ESD) protection devices can have an adverse effect on the performance of high-speed mixed-signal and RF circuits. This paper presents quantitative methodologies to analyze the performance degradation of these circuits due to ESD protection. A detailed S-parameter-based analysis of these high-frequency systems illustrates the utility of the distributed ESD protection scheme and the impact of the parasitics associated with the protection devices. It is shown that a four-stage distributed ESD protection can be beneficial for frequencies up to 10 GHz. In addition, two generalized design optimization methodologies incorporating coplanar waveguides are developed for the distributed structure to achieve a better impedance match over a broad frequency range (0-10 GHz). By using this optimized design, an ESD device with a parasitic capacitance of 200 fF attenuates the RF signal power by only 0.27 dB at 10 GHz. Furthermore, termination schemes are proposed to allow this analysis to be applicable to high-speed digital and mixed-signal systems.
    Preview · Article · Sep 2002 · IEEE Transactions on Electron Devices
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    ABSTRACT: Polysilicon depletion effects show a strong gate length dependence according to experimental p-channel MOS capacitance-voltage (C-V) data. The effect can be influenced not only by gate geometries, but also by dopant profiles in poly-gates. These effects have been modeled and verified using device simulation. Nonuniform dopant distributions in the vertical and lateral direction in the poly-gate cause additional potential drops. The potential drop in the poly-gate becomes critical as the gate geometry is scaled down due to edge and corner depletions resulting from fringing electric fields
    Full-text · Article · Aug 2002 · IEEE Transactions on Electron Devices
  • D.W. Yergeau · R.W. Dutton · R.J.G. Goossens
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    ABSTRACT: Technology computer aided design (TCAD) is concerned with modeling the structural and electrical properties of semiconductor devices. The paper discusses the uses of object oriented (OO) methods to design a new base code for all partial differential equation (PDE) based models
    No preview · Article · May 2002 · IEEE Potentials
  • Source
    Kwang-Hoon Oh · C. Duvvury · K. Banerjee · R.W. Dutton
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    ABSTRACT: ESD failure threshold of NMOS transistors is known to degrade with the use of silicided diffusions owing to insufficient ballast resistance, making them susceptible to current localization, which leads to early ESD failure. It is commonly believed that the gate-to-contact spacing of silicided devices has no impact on the ESD strength. However, experimental results presented in this paper show that the ESD strength depends on the gate-to-contact spacing independent of the silicided process. This paper also presents results of a detailed investigation of the influence of gate-to-source and gate-to-drain contact spacings for a salicided 0.13 μm technology and provides new insight into the behavior of ESD protection devices. It is shown that the reduction in current localization and increase in the power dissipating volume with increase in the gate-to-contact spacings are root causes of this improvement, which implies that even for silicided processes, the gate-to-contact spacing should be carefully considered for efficient and robust ESD protection designs.
    Preview · Conference Paper · Feb 2002
  • Tae-Young Oh · Zhiping Yu · R.W. Dutton
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    ABSTRACT: MOS device scaling into the deep submicron regime inevitably relies on thinner gate oxide and higher substrate doping. Quantum mechanical effects must be considered in device design. This paper presents a density-gradient model which expresses the quantum mechanical effects using macroscopic approximation, and AC analysis based on it. 1D and 2D computer simulations of AC analysis show QM effects on threshold voltage and current with different gate oxide thickness and substrate doping. A simple technique to extract device parameters for circuit design is also presented.
    No preview · Conference Paper · Feb 2002
  • Gaofeng Wang · Xiaoning Qi · Zhiping Yu · R.W. Dutton
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    ABSTRACT: An accurate nonlinear circuit model for metal-insulator-semiconductor (MIS) interconnects is presented based on a device level simulation. The device level simulation gives detailed information regarding field-carrier interactions, semiconductor substrate loss and nonlinearity, as well as slow-wave effect, external bias effect and screening effect of the charged carriers. This model consists of an equivalent transmission line that mimics the energy transport characteristics of the actual MIS interconnect, and provides a generalized nonlinear and electronic tunable circuit model suitable for both small-signal and large-signal analyses.
    No preview · Conference Paper · Feb 2002
  • Source
    Kwang-Hoon Oh · K. Banerjee · C. Duvvury · R.W. Dutton
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    ABSTRACT: Contrary to general understanding, ESD performance of NMOS devices can degrade for shorter channel length transistors in advanced silicided CMOS technologies. In this work, using test structures in a 0.13 /spl mu/m CMOS process, detailed characterization has been carried out for the first time to comprehend and model the physical mechanism causing this degradation. It is shown that the reverse channel length dependence of ESD performance is mainly due to severe non-uniformity in lateral bipolar conduction, which reduces the effective device width. Furthermore, it is demonstrated that substrate bias can be effective in alleviating this reverse channel length effect.
    Preview · Conference Paper · Feb 2002
  • Source
    Chang-Hoon Choi · Zhiping Yu · R.W. Dutton
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    ABSTRACT: Important quantum-mechanical poly quantization effects are demonstrated that reduce inversion capacitance and accentuate short-channel (DIBL) effects in fully depleted double gate SOI devices. Without considering the polysilicon quantization effects, ∼20% over-estimated gate capacitance is predicted with L<sub>g</sub> = 20 nm, t<sub>si</sub> = 5 nm and t<sub>ox</sub> = 1 nm. The polysilicon quantization effect is shown to be enhanced by the drain bias, which implies that DIBL of double-gate SOI is significant due to these effects. The QM effects become worse with increased gate doping, implying ultimate limitations in using polysilicon gates for sub-20 nm DG/FD SOI. Even highly-doped polysilicon gates degrade device performance for sub-20 nm DG/FD SOI due to the polysilicon quantization effects, just as low-doped polysilicon gates degrade performance due to polydepletion effects.
    Preview · Conference Paper · Feb 2002
  • Source
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    ABSTRACT: We explore the generation and effect of phonon hot spots in silicon CMOS devices under steady state operation. The phonon Boltzmann Transport Equation (BTE) is used to extract generated phonon distributions for devices with channel length (L e# ) down to 90 nm. Estimates are made of the impact of phonon hot spots on transistor operation into the L e# range approaching 10 nm. In this scaling limit the dimensions of the phonon hot spot are comparable to the device channel length. It is shown that localized drain region hot spots alter drain characteristics and, in the extreme scaling limit, may affect the resistance and electron injection at the source end, hence the current drive of a device. This is the first study that attempts to quantify non-equilibrium hot phonon effects in ultra-scaled CMOS devices and their implications for future scaling.
    Full-text · Article · Dec 2001
  • C. Ito · K. Banerjee · R.W. Dutton
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    ABSTRACT: Electrostatic discharge (ESD) protection devices can have an adverse effect on the performance of high-speed mixed-signal and RF circuits. This work presents a detailed s-parameter based analysis of the performance of these circuits with special attention to the distributed ESD protection designs. It has been shown that a 4-stage distributed ESD protection can be beneficial at frequencies greater than 3 GHz. Two generalized design optimization methodologies using coplanar waveguides are developed for the distributed structure to achieve a better impedance match over a broad frequency range. By using this optimized design, an ESD device with a parasitic capacitance of 200 fF will attenuate the RF signal power by only 0.27 dB at 10 GHz. A design strategy is also suggested for high-speed mixed-signal ICs.
    No preview · Conference Paper · Oct 2001

Publication Stats

2k Citations
142.06 Total Impact Points

Institutions

  • 1975-2010
    • Stanford University
      • • Department of Electrical Engineering
      • • Center for Integrated Systems
      • • Department of Management Science and Engineering
      • • Department of Applied Physics
      Stanford, California, United States
  • 2001
    • Mission College
      Santa Clara, California, United States
  • 1997
    • Hewlett-Packard
      Palo Alto, California, United States
  • 1990
    • University of California, Berkeley
      Berkeley, California, United States