Dominique Dallet

University of Bordeaux, Burdeos, Aquitaine, France

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Publications (263)56.52 Total impact

  • No preview · Conference Paper · Jan 2016
  • Saeed Mian Qaisar · Reda Yahiaoui · Dominique Dallet
    No preview · Conference Paper · Dec 2015
  • [Show abstract] [Hide abstract] ABSTRACT: An arbitrary waveform generator (AWG) architecture suited for 5G transmission is presented. The digital-to-analog (DA) conversion principle is discussed, underlining its theoretical features toward radio frequency (RF) applications. The signal generation is based on a piecewise linear approximation, resulting from the use of a differential digital coding associated with a custom digital-to-analog converter (DAC), named here the Riemann Pump. The intrinsic performances of this architecture in terms of quantization noise make the Riemann Pump an efficient DAC for multi-carrier applications. Simulations have been carried out on the considered architecture, with a configuration that covers more than 3 GHz bandwidth with a slight oversampling ratio (OSR) and several input bits. Carrier aggregation capabilities are shown with a 5G handset transmission scheme of 10 synchronized 64-QAM modulated signals between 1.8 GHz and 3.6 GHz. This disruptive system exhibits promising performances as for the realization of a 5G handset transmitter with moderate hardware complexity and low power consumption.
    No preview · Article · Dec 2015 · Circuits and Systems II: Express Briefs, IEEE Transactions on
  • Source
    [Show abstract] [Hide abstract] ABSTRACT: Polar Codes can provably achieve the capacity of discrete memoryless channels. In order to make practical, it is necessary to propose efficient hardware decoder architec-tures. In this paper, the first hardware decoder architecture implementing the Soft-output CANcellation (SCAN) decoding algorithm, is presented. This decoder was implemented on Field Programmable Gate Array (FPGA) devices. The proposed architecture is parametrizable for any number of iterations without adding hardware complexity. The SCAN decoder architecture is compared to another soft-output decoder that implements a Belief Propagation (BP) algorithm. The SCAN decoder can reach a higher throughput than a BP decoder, with a lower memory footprint. Moreover, only one iteration with the SCAN algorithm leads to better decoding performance than 50 iterations of the BP algorithm.
    Full-text · Conference Paper · Sep 2015
  • [Show abstract] [Hide abstract] ABSTRACT: The paper introduces an adaptive all-digital architecture for dual-TIADC frequency-response mismatch compensation based on a linear periodic time-varying correction. Parameters of the correction are estimated using correlations of the complex signal derived from the TIADC output. Simulation results of the compensation technique based on real and generated data demonstrate the efficiency of our method.
    No preview · Article · Sep 2015 · Circuits and Systems II: Express Briefs, IEEE Transactions on
  • Source
    Rihab Lahouli · M. Ben-Romdhane · Chiheb Rebai · Dominique Dallet
    [Show abstract] [Hide abstract] ABSTRACT: This paper presents the design and simulation results of a novel mixed baseband stage for a frequency band decomposition (FBD) analog-to-digital converter (ADC) in a multistandard receiver. The proposed FBD-based ADC architecture is flexible with programmable parallel branches composed of discrete time (DT) 4th order single-bit ΣΔ modulators. The mixed baseband architecture uses a single non-programmable anti-aliasing filter (AAF) avoiding the use of an automatic gain control (AGC) circuit. System level analysis proved that the proposed FBD architecture satisfies design specifications of the software defined radio (SDR) receiver. In this paper, the authors focus on the Butterworth AAF filter design for a multistandard receiver. Besides, theoretical analysis of the reconstruction stage for UMTS test case is discussed. It leads to a complicated system of equations and high digital filter orders. To reduce the digital reconstruction stage complexity, the authors propose an optimized digital reconstruction stage architecture design. The demodulation-based digital reconstruction stage using two decimation stages has been implemented using MATLAB/SIMULINK. Technical choices and performances are discussed. The computed signal-to-noise ratio (SNR) of the MATLAB/SIMULINK FBD ADC model is equal to at least 75 dB which satisfies the dynamic range required for UMTS signals. Next to hardware implementation with quantized filters coefficients, the authors implemented their proposition in VHDL in a SysGen environment. The measured SNR of the hardware implementation is equal to 74.08 dB which satisfies the required dynamic range of UMTS signals.
    Full-text · Article · Sep 2015
  • Sahbi Baccar · Timothée Levi · Dominique Dallet · François Barbara
    No preview · Chapter · Aug 2015
  • [Show abstract] [Hide abstract] ABSTRACT: This brief proposes a new digital architecture to compensate for the frequency-response mismatch that is specific to four-channel time-interleaved analog-to-digital converters (quad-TIADCs) using a linear periodic time-varying correction and an adaptive feed-backward design. Estimation of the correction parameters is performed iteratively by solving two linear systems based on correlation values of the real signal from the TIADC output. Problem formulation is well detailed and hardware implementation results demonstrate the efficiency of our method.
    No preview · Article · Aug 2015 · Circuits and Systems II: Express Briefs, IEEE Transactions on
  • R. Lahouli · M. Ben-Romdhane · C. Rebai · D. Dallet
    [Show abstract] [Hide abstract] ABSTRACT: This paper presents the study of phase mismatch in parallel frequency band decomposition (FBD)-based analog-to-digital converter (ADC). This architecture is designed for analog-to-digital conversion of wireless communication signals in a software defined radio (SDR) receiver. It is composed of 6 parallel branches based on discrete-time (DT) ΣΔ modulators using single-bit quantizers. The parallel branches operate on different sub-bandwidths and only needed branches are activated according to the selected standard. The division of the signal channel bandwidth on different sub-bandwidths and the digitization of each sub-bandwidth by one of the parallel branches lead to phase mismatching at the frequency boundaries between the adjacent branches. This paper focuses on the phase mismatch study and its correction in the FBD ΣΔ-based ADC architecture.
    No preview · Article · Jul 2015
  • Daniel Belega · Dario Petri · Dominique Dallet
    [Show abstract] [Hide abstract] ABSTRACT: In this paper the accuracy of the sine-wave frequency estimator returned by an iterative Interpolated Discrete Fourier Transform (IpDFT) algorithm based on a Maximum Sidelobe Decay (MSD) window is analyzed. The expressions for the contribution to the frequency estimation error of either the spectral interference from the sine-wave image component and wideband noise are derived. It is shown that two algorithm iterations ensure the minimum noise sensitivity achievable with the adopted window. The accuracy of the derived expressions is verified by means of computer simulations and validated by experimental results.
    No preview · Article · Jul 2015 · Conference Record - IEEE Instrumentation and Measurement Technology Conference
  • Source
    Rihab Lahouli · Manel Ben-Romdhane · Chiheb Rebai · Dominique Dallet
    [Show abstract] [Hide abstract] ABSTRACT: This paper presents a programmable parallel frequency band decomposition (FBD) ADC which can be used in a software defined radio (SDR) receiver intended for wireless communication standards. The designed parallel ADC architecture is composed of 6 parallel branches based on discrete-time (DT) 4 th order Σ∆ modulators using single-bit quantizers. This paper is focused essentially on the digital reconstruction stage of the designed FBD architecture. The FBD architecture with a demodulation-based digital reconstruction is digitally implemented on a field programmable gate array (FPGA) target from Xilinx Inc.. The frequency conversions performed in the digital reconstruction stage are ensured by a digital oscillator which is carefully tuned to obtain the required frequencies and phases for demodulation and modulation operations. Technical choices and simulation results are discussed. For UMTS use case, the implemented FBD ADC architecture ensures a computed signal-to-noise-ratio (SNR) equal to 74.42 dB. Keywords— Sigma delta modulators, frequency band decomposition architecture, multistandard receiver, digital reconstruction.
    Full-text · Conference Paper · Jul 2015
  • No preview · Article · Jun 2015
  • Daniel Belega · Dario Petri · Dominique Dallet
    [Show abstract] [Hide abstract] ABSTRACT: The paper investigates the effect of the interference due to spectral leakage on the frequency estimates returned by the Interpolated Discrete Fourier Transform (IpDFT) method based on the Maximum Sidelobe Decay (MSD) windows when harmonically distorted sine-waves are analyzed. The expressions for the frequency estimation error due to both the image of the fundamental tone and harmonics, and the frequency estimator variance due to the combined effect of both the above disturbances and wideband noise are derived. The achieved expressions allow us to identify which harmonics significantly contribute to frequency estimation uncertainty. A new IpDFT-based procedure capable to compensate all the significant effects of harmonics on the frequency estimation accuracy is then proposed. The derived theoretical results are verified through computer simulations. Moreover, the accuracy of the proposed procedure is compared with those of other state-of-the-art frequency estimation methods by means of both computer simulations and experimental results.
    No preview · Article · Jun 2015 · Mechanical Systems and Signal Processing
  • Source
    Sahbi Baccar · Timothée Levi · Dominique Dallet · François Barbara
    [Show description] [Hide description] DESCRIPTION: In this paper, an “architectural” description of an instrumentation amplifier (in-amp) is used to simulate its common mode rejection ratio (CMRR) and voltage offset (VOS) in high temperature (HT). The simulations are achieved by using two different models of an industrial op-amp: the familiar SPICE macro-model and a customized VHDL-AMS model. By simulating these two parameters in HT, we evaluate in this work dependency between the op-amp model and the in-amp model. This dependency is described first by reviewing theoretical equations. We compare finally the VHDL-AMS simulation accuracy to the SPICE simulation accuracy in HT.
    Full-text · Research · May 2015
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    [Show abstract] [Hide abstract] ABSTRACT: This paper proposes a new efficient fully digital adaptive method for arbitrary frequency-response mismatches of time-interleaved analog-to-digital converters. It uses FIR filters for signal correction. Correlations between TIADC output data and two different frequency shifted images of these data are used for mismatch estimation. This method has been evaluated in the case of 4-channel TIADCs but it can be extended to any number of channels. Hardware implementation of this new algorithm was carried out and successfully tested at a 2.56 GHz sampling rate on both single tone and dual tone signals. Efficient spur cancellation (30 dB typically) using 3-tap filters for single tone signals and 7-tap filters for dual tone signals has been demonstrated.
    Full-text · Article · Mar 2015
  • Daniel Belega · Dario Petri · Dominique Dallet
    [Show abstract] [Hide abstract] ABSTRACT: In this paper two iterative interpolation algorithms proposed in the scientific literature for estimating the frequency of complex-valued sine-waves are generalized to a generic Maximum Sidelobe Decay (MSD) window in order to achieve highly accurate estimates even when real-valued pure or harmonically distorted sine-waves are analyzed. The analytical expressions for the frequency estimations formulas are derived. Moreover the accuracy achieved when pure, noisy, and noisy and harmonically distorted sine-waves are analyzed is compared with those provided by the classical Interpolated Discrete Fourier Transform (IpDFT) and three-point IpDFT algorithms through computer simulations. The performed comparison allows us to determine in which situations the proposed algorithms can be advantageously used.
    No preview · Article · Jan 2015
  • Sahbi Baccar · Timothée Levi · Dominique Dallet · François Barbara
    [Show abstract] [Hide abstract] ABSTRACT: This chapter deals with the description of a modeling methodology dedicated to simulation of AMS circuits in high temperatures (HT). A behavioral model of an op-amp is developed using VHDL-AMS in order to remedy the inaccuracy of the SPICE model The precision of the model simulation in HT was improved thanks to the VHDL-AMS model. Almost all known op-amp parameters were inserted into the model, which was developed manually. Future work can automate the generation of such a behavioral model to describe the interdependency between different parameters. This is possible by using modern computational intelligence techniques, such as genetic algorithms, or other techniques such as Petri nets or model order reduction.
    No preview · Article · Jan 2015
  • [Show abstract] [Hide abstract] ABSTRACT: An original arbitrary waveform generator (AWG) architecture suited for software radio (SR) transmission is presented. A piecewise linear approximation of the wanted signal is generated thanks to a predefined set of slopes. The digital-to-analog (DA) conversion involved in this operation is based on a differential digital coding which drives a custom digital-to-analog converter (DAC), named here the Riemann Pump. This circuit is in charge of outputting the piecewise linear signal by integration of current steps into a capacitive load, potentially being the input impedance of a power amplifier. Simulations have been carried out on a first design, developed in a GaN technology, with a configuration that covers 1 GHz bandwidth with an oversampling ratio (OSR) of 4 and 3 input bits. The generation of concurrent modulated signals is demonstrated, with a rejection of 30 dBr over the whole band. The system exhibits promising performances as for the realization of a multi-standard concurrent radio frequency transmitter with moderate hardware complexity.
    No preview · Article · Dec 2014
  • [Show abstract] [Hide abstract] ABSTRACT: The trend of communication systems with higher data rates requires complex modulation techniques. To satisfy the stringent linearity requirements of the emitter, linearization techniques have attracted much attention. Many methods are proposed to reduce the effects of nonlinearities. We implemented an analog and digital Cartesian feedback technique in an integrated transmitter in 65-nm CMOS technology. This approach offers flexibility and paves the way for multi-standard linearized RF transmitters.
    No preview · Article · Nov 2014
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    [Show abstract] [Hide abstract] ABSTRACT: Modern Radar systems are very demanding, in terms of absolute electrical performances, flexibility, power consumption and compactness. In the purpose to detect smaller and slower targets, higher levels of resolution with more efficient dynamic performances as larger instantaneous bandwidths are required. Consequently, modern receiver design involves high IF sampling and higher sampling rates. However due to technological limitations, Analog-to-Digital Converters (ADC) are one of the bottlenecks in receiver design, especially when both high frequency operation and high dynamic range are required at the same time, leading to unreasonable increase in power consumption. Multiple core Time Interleaved ADCs (TIADC) are more and more popular since they appear to achieve a better compromise between frequency increase and power consumption while keeping good enough dynamic performances. As a counterpart, due to discrepancies between sampling channels, TIADC suffers from specific degradation of dynamic range related to badly cancelled sub-sampling images: the so-called mismatches. Therefore we propose a new efficient fully digital adaptive method for arbitrary TIADC frequency-response mismatch in order to improve the overall TIADC Spurious Free Dynamic Range (SFDR). It uses FIR filters for signal correction. Correlations between TIADC output data and three different frequency shifted images of these data are used for mismatch estimation. This method has been evaluated in the case of 4-channel TIADCs but it can be extended to any number of channels.
    Full-text · Dataset · Oct 2014

Publication Stats

807 Citations
56.52 Total Impact Points

Institutions

  • 1994-2013
    • University of Bordeaux
      Burdeos, Aquitaine, France
  • 2011-2012
    • Institut Polytechnique de Bordeaux
      • Laboratoire de l’Intégration du Matériau au Système (IMS)
      Talence, Aquitaine, France
  • 2006-2012
    • French National Centre for Scientific Research
      Lutetia Parisorum, Île-de-France, France
  • 2001-2012
    • Université Bordeaux 1
      Talence, Aquitaine, France
  • 2009
    • Polytechnic University of Timisoara
      • Faculty of Electronics and Telecomunications
      Freidorf, Timiş, Romania
  • 2000-2009
    • École Nationale Supérieure d´Électronique et de Radioélectricité de Bordeaux
      Burdeos, Aquitaine, France
  • 2006-2008
    • ENSEIRB - MATMECA
      Talence, Aquitaine, France
  • 2007
    • École Supérieure des Communications de Tunis
      L’Ariana, Ariana, Tunisia
    • University Joseph Fourier - Grenoble 1
      • Laboratoire de Physique Subatomique et Cosmologie
      Grenoble, Rhone-Alpes, France
  • 1995
    • Università degli studi di Parma
      • Department of Information Engineering
      Parma, Emilia-Romagna, Italy