Anil W. Dey

Lund University, Lund, Skåne, Sweden

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Publications (21)120.42 Total impact

  • [Show abstract] [Hide abstract] ABSTRACT: III-V semiconductors have attractive transport properties suitable for low-power, high-speed complementary metal-oxide-semiconductor (CMOS) implementation, but major challenges related to co-integration of III-V n- and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) on low-cost Si substrates have so far hindered their use for large scale logic circuits. Using a novel approach to grow both InAs and InAs/GaSb vertical nanowires of equal length simultaneously in one single growth step, we here demonstrate n- and p-type, III-V MOSFETs monolithically integrated on a Si substrate with high Ion/Ioff ratios using a dual channel, single gate-stack design processed simultaneously for both types of transistors. In addition, we demonstrate fundamental CMOS logic gates, such as inverters and NAND gates, which illustrate the viability of our approach for large scale III-V MOSFET circuits on Si.
    No preview · Article · Nov 2015 · Nano Letters
  • [Show abstract] [Hide abstract] ABSTRACT: In this paper, InAs/GaSb nanowire tunnel field-effect transistors (TFETs) are studied theoretically and experimentally. A 2-band 1-D analytic tunneling model is used to calculate the on- and off-current levels of nanowire TFETs with staggered source/channel band alignment. Experimental results from lateral InAs/GaSb are shown, as well as first results on integration of vertical InAs/GaSb nanowire TFETs on Si substrates.
    No preview · Article · May 2015 · IEEE Journal of the Electron Devices Society
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    [Show abstract] [Hide abstract] ABSTRACT: Temperature dependent electronic properties of GaSb/InAsSb core/shell and GaSb nanowires have been studied. Results from two-probe and four-probe measurements are compared to distinguish between extrinsic (contact-related) and intrinsic (nanowire) properties. It is found that a thin (2?3 nm) InAsSb shell allows low barrier charge carrier injection to the GaSb core, and that the presence of the shell also improves intrinsic nanowire mobility and conductance in comparison to bare GaSb nanowires. Maximum intrinsic field effect mobilities of 200 and 42 cm2 Vs?1 were extracted for the GaSb/InAsSb core/shell and bare-GaSb NWs at room temperature, respectively. The temperature-dependence of the mobility suggests that ionized impurity scattering is the dominant scattering mechanism in bare GaSb while phonon scattering dominates in core/shell nanowires. Top-gated field effect transistors were fabricated based on radial GaSb/InAsSb heterostructure nanowires with shell thicknesses in the range 5?7 nm. The fabricated devices exhibited ambipolar conduction, where the output current was studied as a function of AC gate voltage and frequency. Frequency doubling was experimentally demonstrated up to 20 kHz. The maximum operating frequency was limited by parasitic capacitance associated with the measurement chip geometry.
    Full-text · Article · Sep 2014 · Nanotechnology
  • [Show abstract] [Hide abstract] ABSTRACT: The package density is one main motivation for transistor scaling. It has been suggested that alternative paths need to be considered for scaling of future high-speed low-power devices. For this reason, we consider tunnel field-effect transistors as a radial device in a vertical nanowire architecture. TFETs have already been demonstrated with metal-oxide-semiconductor field-effect transistor (MOSFET) like current levels. The benefit of a vertical nanowire architecture is to enable high drive currents without sacrificing neither the chip area footprint nor the device electrostatics. In this paper, we explore the key elements of a radial tunnel field-effect transistor (rTFET) and the impact on the device performance based on experimental data from both Esaki diodes and TFETs in a radial nanowire architecture.
    No preview · Conference Paper · Jun 2014
  • [Show abstract] [Hide abstract] ABSTRACT: The ever-growing demand on high-performance electronics has generated transistors with very impressive figures of merit. The continued scaling of the supply voltage of field-effect transistors, such as tunnel field-effect transistors (TFETs), requires the implementation of advanced transistor architectures including FinFETs and nanowire devices. Moreover, integration of novel materials with high electron mobilities, such as III-V semiconductors and graphene, are also being considered to further enhance the device properties. In nanowire devices, boosting the drive current at a fixed supply voltage or maintaining a constant drive current at a reduced supply voltage may be achieved by increasing the cross-sectional area of a device, however at the cost of deteriorated electrostatics. A gate-all-around nanowire device architecture is the most favorable electrostatic configuration to suppress short channel effects, however, the arrangement of arrays of parallel vertical nanowires to address the drive current predicament will require additional chip area. The use of a core-shell nanowire with a radial heterojunction in a transistor architecture provides an attractive means to address the drive current issue without compromising neither chip area nor device electrostatics. In addition to design advantages of a radial transistor architecture, we in this work illustrate the benefit in terms of drive current per unit chip area and compare the experimental data for axial GaSb/InAs Esaki diodes and TFETs to their radial counterparts and normalize the electrical data to the largest cross-sectional area of the nanowire, i.e. the occupied chip area, assuming a vertical device geometry. Our data on lateral devices show that radial Esaki diodes deliver almost 7 times higher peak current, Jpeak = 2310 kA/cm2, than the maximum peak current of axial GaSb/InAs(Sb) Esaki diodes per unit chip area. The radial TFETs also deliver high peak current densities Jpeak = 1210 kA/cm2 while their axial counterparts at most carry Jpeak = 77 kA/cm2, normalized to the largest cross-sectional area of the nanowire.
    No preview · Article · Nov 2013 · Nano Letters
  • [Show abstract] [Hide abstract] ABSTRACT: In order to reduce the power consumption, III-V semiconductor materials may be considered to lower the supply voltage. Reports on III-V complementary metal-oxide semiconductor (CMOS) circuitry are scarce and only few devices have been demonstrated to date. We have previously demonstrated III-V CMOS inverters by integrating n-InAs and p-GaSb segments in a single nanowire. Since the design was intended for functionality demonstration, using long gate lengths and a not intentionally doped channel, the operating frequency of the inverters was found to be limited by a large output parasitic capacitance on the pad and the low drive-currents of the GaSb pFET, as compared to the InAs nFET. We have previously shown that the performance of InAs nanowire nFETs can show large values of gm and ION through scaling and device design optimization. We here demonstrate steps to increase the performance of GaSb nanowire pFETs in a similar fashion.
    No preview · Conference Paper · Jun 2013
  • [Show abstract] [Hide abstract] ABSTRACT: We present electrical characterization of GaSb/InAs(Sb) nanowire tunnel field-effect transistors. The broken band alignment of the GaSb/InAs(Sb) heterostructure is exploited to allow for interband tunneling without a barrier, leading to high on-current levels. We report a maximum drive current of 310 $muhbox{A}/muhbox{m}$ at $V_{DS} = hbox{0.5} hbox{V}$. Devices with scaled gate oxides display transconductances up to $g_{m} = hbox{250} hbox{mS/mm}$ at $V_{DS} = hbox{300} hbox{mV}$, which are normalized to the nanowire circumference at the axial heterojunction.
    No preview · Article · Feb 2013 · IEEE Electron Device Letters
  • [Show abstract] [Hide abstract] ABSTRACT: III-V semiconductors have so far predominately been employed for n-type transistors in high-frequency applications. This development is based on the advantageous transport properties and the large variety of heterostructure combinations in the family of III-V semiconductors. In contrast, reports on p-type devices with high hole mobility suitable for complementary metal-oxide-semiconductor (CMOS) circuits for low-power operation are scarce. In addition, the difficulty to integrate both n- and p-type devices on the same substrate without the use of complex buffer layers has hampered the development of III-V based digital logic. Here, inverters fabricated from single n-InAs/p-GaSb heterostructure nanowires are demonstrated in a simple processing scheme. Using undoped segments and aggressively scaled high-κ dielectric, enhancement mode operation suitable for digital logic is obtained for both types of transistors. State-of-the-art on- and off-state characteristics are obtained and the individual long-channel n- and p-type transistors exhibit minimum subthreshold swings of SS = 98 mV/dec and SS = 400 mV/dec, respectively, at V(ds) = 0.5 V. Inverter characteristics display a full signal swing and maximum gain of 10.5 with a small device-to-device variability. Complete inversion is measured at low frequencies although large parasitic capacitances deform the waveform at higher frequencies.
    No preview · Article · Oct 2012 · Nano Letters
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    [Show abstract] [Hide abstract] ABSTRACT: The effect of various doping profiles on the electronic transport in GaSb/InAs(Sb) nanowire tunnel diodes is investigated. Zn-doping of the GaSb segment increases both the peak current density and the current level in reverse bias. Top-gated diodes exhibit peak current modulation with a threshold voltage which can be controlled by Zn-doping the InAs(Sb) segment. By intentionally n-doping the InAs(Sb) segment degenerate doping on both sides of the heterojunction can be achieved, as well as tunnel diodes with peak current of 420 kA/cm2 at VDS = 0.16 V and a record-high current density of 3.6 MA/cm2 at VDS = −0.5 V.
    Full-text · Article · Jul 2012 · Applied Physics Letters
  • [Show abstract] [Hide abstract] ABSTRACT: Steep-slope devices, such as tunnel field-effect transistors (TFETs), have recently gained interest due to their potential for low power operation at room temperature. The devices are based on inter-band tunneling which could limit the on-current since the charge carriers must tunnel through a barrier to traverse the device. The InAs/GaSb heterostructure forms a broken type II band alignment which enables inter-band tunneling without a barrier, allowing high on-currents. We have recently demonstrated high current density (I ON,reverse = 17.5 mA/mum 2) nanowire Esaki diodes and in this work we investigate the potential of InAs/GaSb heterostructure nanowires to operate as TFETs. We present device characterization of InAs 0.85Sb 0.15/GaSb nanowire TFETs, which exhibit record-high on-current levels.
    No preview · Conference Paper · Jun 2012
  • [Show abstract] [Hide abstract] ABSTRACT: In this letter, we present a 15-nm-diameter InAs nanowire MOSFET with excellent on and off characteristics. An n-i-n doping profile was used to reduce the source and drain resistances, and an Al2O3/HfO2 bilayer was introduced in the high-kappa process. The nanowires exhibit high drive currents, up to 1.25 A/mm, normalized to the nanowire circumference, and current densities up to 34 MA/cm(2) (V-D = 0.5 V). For a nominal L-G = 100 nm, we observe an extrinsic transconductance (g(m)) of 1.23 S/mm and a subthreshold swing of 93 mV/decade at V-D = 10 mV.
    No preview · Article · Jun 2012 · IEEE Electron Device Letters
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    [Show abstract] [Hide abstract] ABSTRACT: We selectively etch axial GaSb/InAsSb nanowires locally at the heterojunction using in situ thermal annealing. This results in broken-gap tunnel diodes with a significantly reduced diameter only in the tunnel region. The etching mechanism proceeds by material removal from unstabilized 111A facets which may form due to a reduced thermal stability at the heterointerface of GaSb/InAsSb nanowires. By removing the parallel conduction path between the InAsSb shell and nanowire the selective etching strongly improves the device performance. This is demonstrated in fabricated tunnel diodes that exhibit a peak-to-valley ratio of 1.3 and high peak current densities (8.1 kA/cm(2)). (C) 2011 American Institute of Physics. [doi: 10.1063/1.3662009]
    Full-text · Article · Nov 2011 · Applied Physics Letters
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    [Show abstract] [Hide abstract] ABSTRACT: In this work, the nucleation and growth of InAs nanowires on patterned SiO(2)/Si(111) substrates is studied. It is found that the nanowire yield is strongly dependent on the size of the etched holes in the SiO(2), where openings smaller than 180 nm lead to a substantial decrease in nucleation yield, while openings larger than ≈500nm promote nucleation of crystallites rather than nanowires. We propose that this is a result of indium particle formation prior to nanowire growth, where the size of the indium particles, under constant growth parameters, is strongly influenced by the size of the openings in the SiO(2) film. Nanowires overgrowing the etched holes, eventually leading to a merging of neighboring nanowires, shed light into the growth mechanism.
    Full-text · Article · Nov 2011 · Journal of Crystal Growth
  • [Show abstract] [Hide abstract] ABSTRACT: Switching of the group-III element in III-V nanowire heterostructures is difficult due to the high solubility of group Ill atoms in the Au seed particle. In addition, switching from Sb to a different group-V element has not been achieved in binary materials, largely due to its high solubility in Au. In metal - organic vapor phase epitaxy (MOVPE) growth, the use of Sb precursors presents further complications due to reactor background contamination. In this paper, we demonstrate growth of GaSb/InAs(Sb) nanowire heterostructures with potential applications in tunneling devices and study the processes occurring during the transition from GaSb to InAs growth. We show how the heterostructure can be grown with a sharp transition by taking advantage of a growth stop, which occurs naturally; as the Au seed particle is emptied of 6 a and filled with In The remaining Sb background in the reactor during the InAs growth results in a finite Sb incorporation into this segment This has the advantage of suppressing stacking faults in the InAs(Sb) segment, making the entire heterostructure a single zincblende crystal.
    No preview · Article · Oct 2011 · Crystal Growth & Design
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    [Show abstract] [Hide abstract] ABSTRACT: We present electrical characterization of broken gap GaSb-InAsSb nanowire heterojunctions. Esaki diode characteristics with maximum reverse current of 1750 kA/cm(2) at 0.50 V, maximum peak current of 67 kA/cm(2) at 0.11 V, and peak-to-valley ratio (PVR) of 2.1 are obtained at room temperature. The reverse current density is comparable to that of state-of-the-art tunnel diodes based on heavily doped p-n junctions. However, the GaSb-InAsSb diodes investigated in this work do not rely on heavy doping, which permits studies of transport mechanisms in simple transistor structures processed with high-κ gate dielectrics and top-gates. Such processing results in devices with improved PVR (3.5) and stability of the electrical properties.
    Full-text · Article · Sep 2011 · Nano Letters
  • [Show abstract] [Hide abstract] ABSTRACT: We report a systematic study of the relationship between crystal quality and electrical properties of InAs nanowires grown by MOVPE and MBE, with crystal structure varying from wurtzite to zinc blende. We find that mixtures of these phases can exhibit up to 2 orders of magnitude higher resistivity than single-phase nanowires, with a temperature-activated transport mechanism. However, it is also found that defects in the form of stacking faults and twin planes do not significantly affect the resistivity. These findings are important for nanowire-based devices, where uncontrolled formation of particular polytype mixtures may lead to unacceptable device variability.
    No preview · Article · Jun 2011 · Nano Letters
  • [Show abstract] [Hide abstract] ABSTRACT: InAs is an attractive channel material for III-V nanowire MOSFETs and early prototype high performance nanowire transistors have been demonstrated 1. As the gate length is reduced, the nanowire diameter must be scaled quite aggressively in order to suppress short-channel effects 2. However, a reduction in transconductance (g m) and drive current (I ON) could be expected due to increased surface scattering for thin wires. We present data for the device properties of thin InAs nanowires, with diameters in the 15 nm range, and investigate possible improvements of the performance focusing on transistor applications. In order to boost I ON, the source and drain resistance need to be reduced. Several doping sources were therefore evaluated in the study, among them selenium (Se), tin (Sn) and sulphur (S) to form n-i-n structures. We report very high current densities, up to 33 MA/cm 2, comparable to modern HEMTs 3, and a normalized transconductance of 1.8 S/mm for a nanowire with an intrinsic segment of nominally 150 nm and a diameter of 15 nm.
    No preview · Conference Paper · Jun 2011
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    [Show abstract] [Hide abstract] ABSTRACT: Group III-V nanowires offer the exciting possibility of epitaxial growth on a wide variety of substrates, most importantly silicon. To ensure compatibility with Si technology, catalyst-free growth schemes are of particular relevance, to avoid impurities from the catalysts. While this type of growth is well-documented and some aspects are described, no detailed understanding of the nucleation and the growth mechanism has been developed. By combining a series of growth experiments using metal-organic vapor phase epitaxy, as well as detailed in situ surface imaging and spectroscopy, we gain deeper insight into nucleation and growth of self-seeded III-V nanowires. By this mechanism most work available in literature concerning this field can be described.
    Full-text · Article · Oct 2010 · Nano Letters
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    [Show abstract] [Hide abstract] ABSTRACT: This letter presents dc characteristics and low-frequency noise (LFN) measurements on single vertical InAs nanowire MOSFETs with 35-nm gate length and HfO<sub>2</sub> high-?? dielectric. The average normalized transconductance for three devices is 0.16 S/mm, with a subthreshold slope of 130 mV/decade. At 10 Hz, the normalized noise power SI / Id <sup>2</sup> measures 7.3 ?? 10<sup>-7</sup> Hz<sup>-1</sup>. Moreover, the material-dependent Hooge's parameter at room temperature is estimated to be 4.2 ?? 10<sup>-3</sup>.
    Full-text · Article · Jun 2010 · IEEE Electron Device Letters
  • [Show abstract] [Hide abstract] ABSTRACT: We report on RF characterization of vertical, 100-nm-gate length InAs nanowire MOSFETs, utilizing wrap-gate technology and Al2O3 high-K gate oxide. The transistors show ft=5.6 GHz and fmax=22 GHz, mainly limited by parasitic capacitances. The RF device performance is described using a hybrid-π model taking hole generation at the drain into account. Electrostatic modeling of the parasitic capacitances for arrays of vertical nanowires indicates that a strong reduction in extrinsic capacitances can be achieved for devices with a small inter-wire separation.
    No preview · Article · May 2010 · Conference Proceedings - International Conference on Indium Phosphide and Related Materials