W.-J. Hsu

University of Southern California, Los Angeles, California, United States

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Publications (11)10.03 Total impact

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    ABSTRACT: A systematic approach to predict semiconductor degradation effects using reliability simulation is described. The DC degradation monitor is first extracted during transient circuit simulation. An AC degradation factor is then used to determine circuit performance degradation. By using these techniques on the design of CMOS components, proper long-term reliability can be achieved for high-speed circuits. Experimental results on digital circuits using an industrial submicrometer technology demonstrate the effectiveness of this approach in reliable VLSI circuit design. Results on two-input NAND gates, DRAM precharging circuit, and SRAM control circuits are presented
    No preview · Article · Apr 1992 · IEEE Journal of Solid-State Circuits
  • W.-J. Hsu · B.J. Sheu · S.M. Gowda
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    ABSTRACT: A systematic approach to test analog array-processor neural chips is presented. Unique testing problems for analog neural chips are described and effective solutions are discussed. Based on the hierarchical methodology, testing of analog array-processor neural chips can be systematically addressed. The test results for programmable analog neural chips fabricated by a 2-μm CMOS process are presented. These chips contain 25 neurons and 1600 synapses
    No preview · Conference Paper · Nov 1991
  • W.-J. Hsu · S.M. Gowda · B.J. Sheu · Chang-Gyu Hwang
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    ABSTRACT: The development of high-reliability integrated circuits requires accurate prediction of circuit lifetime including dynamic stress effects. A systematic approach for classifying dynamic stress conditions and accounting for AC-induced excessive hot-carrier damage using an effective degradation factor is described. An equivalent DC degradation monitor is simulated using a two-pass approach. Experimental results on digital circuits, including memory circuits, are presented. In particular, results are presented on substrate currents in NAND gates, degradation in precharging current, and a SRAM cell and peripheral circuits
    No preview · Conference Paper · Jun 1991
  • W.-J. Hsu · Bing J. Sheu · Sudhir M. Gowda
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    ABSTRACT: An iterative simulation method of predicting the impact of progressive device degradation on circuit performance due to common microelectronic failure mechanisms is described. Simulation schemes for the lifetime prediction of ASICs as well as modeling requirements for accurate and efficient simulation are presented. These simulation schemes have been implemented in the prototype reliability simulator RELY to evaluate circuit performance degradation and provide reliability enhancement information. Hot-carrier effects on submicrometer digital and analog circuits are used to demonstrate the approach. Experimental results on precharging circuitry for sense amplifiers and operational amplifiers are presented
    No preview · Article · Apr 1991 · IEEE Journal of Solid-State Circuits
  • W.-J. Hsu · S.M. Gowda · B.J. Sheu
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    ABSTRACT: The use of reliability assurance and enhancement of integrated circuits in the design of high-performance electronic systems is discussed. Circuit simulators with embedded degradation models can be utilized to accurately predict VLSI reliability due to hot-carrier effects and electromigration. Basic design methods for constructing digital and analog circuit blocks with adequate built-in reliability are presented. Lifetime for DRAM circuitries and operational amplifiers can be significantly increased through these novel simulation techniques. Several practical VLSI design examples using an integrated-circuit reliability simulator are discussed
    No preview · Conference Paper · Jun 1990
  • B.J. Sheu · W.-J. Hsu · V. Tyree
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    ABSTRACT: An integrated-circuit reliability simulator has been developed. Model parameters for the reliability simulation are obtained through accelerated tests on specially designed test structures. The design of several test chips and associated experimental results are presented. Reliability simulations are described at the detailed circuit-design level using the SPICE circuit simulator or its derivatives as the key module. A computer-automated characterization system is necessary to extract parameter values for the new degradation models
    No preview · Conference Paper · Feb 1990
  • W.-J. Hsu · B.J. Sheu · V.C. Tyree
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    ABSTRACT: A novel approach to the design of digital and analog VLSI with built-in reliability is presented. Physics-based reliability models for key failure mechanisms in VLSI circuits are used to achieve accurate and efficient circuit-level reliability prediction and improvement. A prototype integrated-circuit reliability simulator (RELY) and experimental results on hot-carrier damage and metal electromigration effects are presented
    No preview · Conference Paper · Nov 1989
  • B.J. Sheu · W.-J. Hsu · V.C. Tyree
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    ABSTRACT: It is noted that challenges to the improvement of quality and reliability in VLSI circuits come from the rapid advances of CMOS fabrication technologies. To provide circuit designers with the means for designing circuits that can utilize the full reliability potential of the fabrication technology, a circuit reliability simulator has been developed. Key reliability concerns in VLSI circuits and microsystems include hot-carrier damage, electromigration, time-dependent dielectric breakdown, packaging damage, radiation damage, and contamination of oxides and junctions. The authors describe several salient modeling requirements for reliability simulations at the detailed circuit design level using the SPICE circuit simulator as the key module
    No preview · Conference Paper · Jul 1989
  • Bing J. Sheu · W.-J. Hsu · Bang W. Lee
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    ABSTRACT: A prototype very-large-scale integrated circuit (VLSI) reliability simulator is described. Software modules for hot-carrier effects have been developed. Popular substrate current models are implemented in the simulator. Experiments were performed to establish the relationship between transistor model parameter changes and the substrate current level. The circuit reliability simulation techniques can be extended to include dielectric breakdown and interconnect electromigration effects
    No preview · Article · May 1989 · IEEE Journal of Solid-State Circuits
  • W.-J. Hsu · C.-C. Shih · B.J. Sheu
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    ABSTRACT: A novel reliability simulator and its associated circuit-level degradation models with automated parameter extraction procedures for VLSI circuits have been developed. This circuit reliability modeling and simulation environment can serve as a bridge between the system and device reliability. Performance and lifetime of digital and analog ICs can be optimized through the usage of this reliability simulator
    No preview · Conference Paper · Jun 1988
  • Bing J. Sheu · W.-J. Hsu · Ping K. Ko
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    ABSTRACT: The development of an MOS transistor charge and capacitance model for the analysis and design of VLSI circuits is described. The total stored charge in each of the gate, bulk, and channel regions is obtained by integrating the distributed charge densities over the thin-oxide area. Charge conservation is guaranteed in this model by using the terminal charges as the state variables. The capacitance expressions have the nonreciprocal property. Partition of channel charge into the drain and source components is 40/60 in the saturation region. In the triode region, this partition changes asymptotically to 50/50 as the gate voltage increases. The carrier-velocity saturation effect is incorporated through both the modification of channel quasi-Fermi level and the determination of drain saturation voltage. Implementation of the model in the SPICE circuit simulator has been achieved. Modeled results compare well with experimental data for transistors with channel lengths as small as 0.75 μm
    No preview · Article · May 1988 · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems