D.S.H. Chan

National University of Singapore, Singapore, Singapore

Are you D.S.H. Chan?

Claim your profile

Publications (164)224.76 Total impact

  • Y. F. Lu · M. H. Hong · D. S. H. Chan · T. S. Low
    [Show abstract] [Hide abstract]
    ABSTRACT: Excimer laser ablation is applied in the deflashing and demarking of IC packages. It is found that mold flash filled in the interface holes of IC leadframe can be removed completely by the laser deflashing in a short period of time. With appropriate selection of laser parameters, deflashing quality and efficiency can be greatly improved. The laser deflashing is more efficient for higher pin count packages. It is a superior alternative in future applications. In laser demarking, ink marks on package surfaces can also be removed completely in a short time. The surface after the processing has good conditions for remarking. The package remarking shows good permanency. The lifetime for good marking is much longer for IC packages after the laser demarking than those after hydrogen flame-off. Laser processing can be used to replace hydrogen flame-off in the ink printing of IC packages for high efficiency and safety.
    No preview · Article · Jan 2011 · MRS Online Proceeding Library
  • Y. F. Lu · W. D. Song · M. H. Hong · D. S. H. Chan · T. S. Low

    No preview · Article · Jan 2011 · MRS Online Proceeding Library
  • Y.F. Lu · M. Meng · M.H. Hong · T.S. Low · D.S.H. Chan
    [Show abstract] [Hide abstract]
    ABSTRACT: Closed-loop control and real-time monitoring of pulsed excimer laser cleaning and ablation have been realised by software and hardware design and development. The audible acoustic wave generated during excimer laser surface cleaning and ablation has been used as the feedback signal for the automatic control system of laser-surface interaction. Man–machine interface for laser operation and acoustic monitoring has been developed with LabVIEW 4.1 under Windows 95 environment. This system has been used to control and monitor laser cleaning and ablation processes in real-time and proven to successfully meet the requirements in our study. By database exchange, this automatic control system can also be applied to control drilling and materials removing.
    No preview · Article · Jan 2011 · MRS Online Proceeding Library
  • Y. F. Lu · Z. B. Tao · M. H. Hong · D.S.H. Chan · T.S. Low

    No preview · Article · Jan 2011 · MRS Online Proceeding Library
  • Wei He · Jing Pu · D.S.H. Chan · Byung Jin Cho
    [Show abstract] [Hide abstract]
    ABSTRACT: Lanthanum-based high-kappa dielectrics ( LaAlO x and LaHfO x ) are systematically investigated as blocking oxide in charge-trap-type flash memory devices. Compared to Al<sub>2</sub>O<sub>3</sub> blocking oxide, LaAlO x not only exhibits faster program speed, wider V <sub>th</sub> window, and more robustness to voltage stress but also has better retention performance when the temperature is below 120degC, particularly at 85degC . In contrast, although further improvements in V <sub>th</sub> window and robustness are achieved using a higher permittivity dielectric LaHfO x , its retention performance is poor. It is found that the retention property is critically determined by the conduction band offset of a blocking oxide. This is caused by the shallow trapping energy depth inside the nitride which is calculated to be 0.6-0.75 eV below the conduction band edge.
    No preview · Article · Dec 2009 · IEEE Transactions on Electron Devices
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: We demonstrated, for the first time, p-MOSFETs (L<sub>G</sub> ges 40 nm) with SiGe/Si core/shell channel integrated on bulk Si using a CMOS-compatible top-down processes. The Omega-shaped nanowire (NW)-like channels comprised of ~12-nm-thick inner SiGe core and 4-nm-thick outer Si shell. The devices exhibited good subthreshold characteristics (with SS ~128 mV/dec), suggesting successful surface passivation of the SiGe NW body by the outer Si capping layer. Drive currents of ~167 muA/mum is achieved, which is 15% enhancement over the reference Si-channel devices fabricated by the same process. Double g<sub>m</sub> peaks are observed at low drain bias for the core/shell SiGe NW devices, confirming the quantum confinement of holes in the SiGe inner core.
    Full-text · Article · May 2009 · IEEE Electron Device Letters
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: A significant increase in open circuit voltage (VOC) is obtained in the polymer-fullerene bulk heterojunction solar cell by using the e-beam deposited Al cathode. Compared with the device with the thermal evaporated Al cathode, an obvious enhancement of VOC from 596 to 664 mV is obtained, which makes the overall device power conversion efficiency improved by 12.4% (from 3.79% to 4.26%). Electrical characterizations suggest that the energetic particles in the e-beam deposition induce deep interface hole traps in the poly(3-hexylthiophene-2,5-diyl) (P3HT), while leaving the fullerene unaffected. The deep trapped holes near the P3HT/cathode interface can induce the image negative charges in the cathode and thus form “dipoles.” These dipoles lead to the lowering of the Al effective work function and cause the enhancement of VOC.
    Full-text · Article · Mar 2009 · Applied Physics Letters
  • Source
    Y. Jiang · T.Y. Liow · N. Singh · L.H. Tan · G.Q. Lo · D. S. H. Chan · D.L. Kwong
    [Show abstract] [Hide abstract]
    ABSTRACT: A simple and cost-effective single metal gate scheme was successfully demonstrated to form gate-all-around (GAA) nanowire FETs with optimized dual V<sub>T</sub> for low power CMOS applications. FUSI gate-induced stress effects were shown to be of great relevance to device performance. At an I<sub>Off</sub> of 20 pA/mum, superior I<sub>On</sub> of 1180 and 405 muA/mum were obtained for NFETs and PFETs at a V<sub>DD</sub> of 1.2 V.
    Preview · Conference Paper · Jan 2009
  • Source
    Y. Jiang · N. Singh · T. Y. Liow · G. Q. Lo · D. S. H. Chan · D. L. Kwong
    [Show abstract] [Hide abstract]
    ABSTRACT: In this work, we investigate the effect of energy band profile modulation on carrier backscattering in SiGe nanowire (SGNW) heterojunction p-channel field effect transistors. The energy band profile is modulated by increasing the Ge mole fraction in nanowire channels as compared to source/drain regions using the pattern-dependent Ge condensation technique. The carrier backscattering characteristics of the fabricated heterojunction p-type SGNW transistors, extracted using a temperature-dependent analytical model, exhibited a decrease of 19% in hole backscattering coefficient in comparison to the reference planar devices with uniform Ge concentration. The reduction in backscattering coefficient is attributed to KT/q barrier layer thinning of the source-to-channel barrier for the holes as a result of the modulation in energy band profile caused by variation in Ge concentration.
    Preview · Article · Dec 2008 · Applied Physics Letters
  • [Show abstract] [Hide abstract]
    ABSTRACT: Near-infrared photon emission spectra were obtained from the frontside of silicon nMOSFETs and pMOSFETs with a gate length of 0.13 mum and biased into saturation. These spectra were obtained using a high sensitivity in-lens spectroscopic photon emission microscope. Frontside NIR photon emission spectroscopy are performed on 0.13 mum saturated nMOSFETs and pMOSFETs at different gate and drain bias. The nMOSFETs photon emission spectra obtained are significantly different from some previously reported photon emission spectra. The NIR photon emission spectra of the nMOSFETs and pMOSFETs have similar peaks and suggest that the electric field condition in the channels of the nMOSFETs and pMOSFETs are similar.
    No preview · Conference Paper · Aug 2008
  • [Show abstract] [Hide abstract]
    ABSTRACT: A multilayer structure of copper phthalocyanine/poly(3-hexylthiophene-2,5-diyl): [6,6]-phenyl- C <sub>61</sub> -butyric acid methyl ester (CuPc/P3HT:PCBM) is used to extend the light absorption spectrum covering almost the entire visible spectrum. To maximize the light absorption, the total number of excitons created in the multilayer structure as a function of layer thickness of both CuPc and P3HT:PCBM is simulated by using the optical transfer matrix formalism. The solar cells with a device structure of ITO/PEDOT:PSS/CuPc/P3HT:PCBM/Al are fabricated with different layers thicknesses. The optimized solar cell with a high short circuit current density of 12.54 mA / cm <sup>2</sup> and power conversion efficiency as high as 4.13% is achieved, owing to the utilization of the second optical interference peak in the multilayer structure for the enhanced light absorption.
    No preview · Article · Aug 2008 · Applied Physics Letters
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: A simple method is developed to make an interpenetrating network of poly(3-hexylthiophene-2,5-diyl) (P3HT) and fullerene (C60) by mixing P3HT solution with a thermal initiator 2,2′-azobis(isobutyronitrile) (AIBN). After mild annealing, the release of nitrogen from AIBN increases the roughness of P3HT dramatically. Significant photoluminescence quenching between the roughened donor P3HT and overlaying acceptor C60 is related to the significant increment of donor-acceptor interfacial areas. Based on this interpenetrated network of P3HT/C60, more than threefold increase in the photovoltaic efficiency of devices is achieved compared with bilayer structure. Fill factor is also improved, implying good percolation path in this heterojunction structure.
    Full-text · Article · Jul 2008 · Applied Physics Letters
  • Source
    Y. Jiang · T.Y. Liow · N. Singh · L.H. Tan · G.Q. Lo · D.S.H. Chan · D.L. Kwong
    [Show abstract] [Hide abstract]
    ABSTRACT: Parasitic S/D resistances in extremely scaled GAA nanowire devices can pathologically limit the device drive current performance. We demonstrate for the first time, that S/D extension dopant profile engineering together with successful integration of low resistivity metallic nanowire contacts greatly reduces parasitic resistances. This allows 8 nm gate length GAA nanowire devices in this work to attain record-high drive currents of 3740 muA/mum.
    Preview · Conference Paper · Jul 2008
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: A top-down approach of forming SiGe-nanowire (SGNW) MOSFET, with Ge concentration modulated along the source/drain (Si<sub>0.7</sub>Ge<sub>0.3</sub>) to channel (Si<sub>0.3</sub>Ge<sub>0.7</sub>) regions, is presented. Fabricated by utilizing a pattern-size-dependent Ge-condensation technique, the SGNW heterostructure PMOS device exhibits 4.5times enhancement in the drive current and transconductance (G<sub>m</sub>) as compared to the homojunction planar device (Si<sub>0.7</sub>Ge<sub>0.3</sub>). This large enhancement can be attributed to several factors including Omega-gated nanowire structure, enhanced hole injection efficiency (due to valence band offset), and improved hole mobility (due to compressive strain and Ge enrichment in the nanowire channel).
    Full-text · Article · Jul 2008 · IEEE Electron Device Letters
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: We proposed and demonstrated a simple tandem structure of organic photovoltaic (PV) cell for efficient light harvesting. In this device structure, a soluble fullerene derivative of [6,6]-phenyl-C61-butyric acid methyl ester (PCBM) is employed simultaneously to form a bilayer heterojunction PV subcell with the underlying copper phthalocyanine (CuPc) and a bulk heterojunction PV subcell with blended poly(3-hexylthiophene-2,5-diyl) (P3HT). In comparison with the conventional tandem structure, the omission of the semitransparent intercellular connection layer reduces the complexity of the device and the light loss. The enhanced short circuit current density (JSC = 8.63 mA/cm2) and power conversion efficiency (PCE) (2.79%) of the tandem structure are nearly the sum of those of the stand-alone cells of CuPc/PCBM (JSC = 2.09 mA/cm2, PCE = 0.43%) and P3HT:PCBM (JSC = 6.87 mA/cm2, PCE = 2.50%).
    Full-text · Article · Feb 2008 · Applied Physics Letters
  • [Show abstract] [Hide abstract]
    ABSTRACT: Insertion of gold nanoparticles (GNPs) layer between the indium tin oxide (ITO) and the photoactive polymer by simple spin-coating method is found to improve the photovoltaic effects of solar cells significantly. Cross sectional SEM image provides direct evidence that GNPs layer acts as a pure buffer layer in our devices. The improvement of the device performance is due to good transmission, high work function, good conductivity, and ultra-smooth surface roughness of GNPs layer. GNPs layer can act as a promising buffer layer to facilitate hole collection from polymer donor towards ITO anode.
    No preview · Article · Feb 2008 · Chemical Physics Letters
  • Jing Pu · D.S.H. Chan · Byung Jin Cho
    [Show abstract] [Hide abstract]
    ABSTRACT: We propose one novel approach on engineering floating gate (FG) of Flash memory cell: carbon incorporation into polysilicon FG. This technique demonstrated improvement in retention and larger program/erase Vth window, especially for smaller capacitance coupling ratio cell which is important for future scaled Flash memory cells.
    No preview · Article · Jan 2008
  • [Show abstract] [Hide abstract]
    ABSTRACT: We report a nonvolatile, write-once-read-many-times (WORM) memory device based on a simple organic-inorganic heterojunction. The organic-based hybrid used is 9,9-dihexylfluorene and Eu-complexed benzoate, which contains both electron-donor (9, 9″ -dihexylfluorene) and electron-acceptor (europium complex) groups. Under current-voltage testing, the device is able to switch from one initial nonconducting state to a conducting state once a threshold voltage is reached. Diode rectifying characteristics, with a current ratio of four orders of magnitude, is also observed after the device is turned on, which is essential to address one memory cell in large passive matrix circuits.
    No preview · Article · Jan 2008 · Journal of The Electrochemical Society
  • [Show abstract] [Hide abstract]
    ABSTRACT: In this paper, we report for the first time a novel dual metal gate (MG) integration process for gate-first CMOS platform by utilizing the intermixing (InM) of laminated ultra-thin metal layers during high-temperature annealing at 1000 °C. In this process, an ultra-thin (∼2 nm) TaN film is first deposited on gate dielectric as a buffer layer. Preferable laminated metal stacks for NMOS and PMOS are then formed on a same wafer through a selective wet-etching process in which the gate dielectric is protected by the TaN buffer layer. Dual work function for CMOS can finally be achieved by the intermixing of the laminated metal films during the S/D activation annealing. To demonstrate this process, prototype metal stacks of TaN/Tb/TaN (NMOS) and TaN/Ti/HfN (PMOS) has been integrated on a single wafer, with WF of 4.15 and 4.72 eV achieved, respectively. Threshold voltage (Vth) adjustment and transistor characteristics on high-k HfTaON dielectric are also studied.
    No preview · Article · Nov 2007 · Solid-State Electronics
  • Source
    J. F. Kang · H. Y. Yu · C. Ren · N. Sa · H. Yang · M.-F. Li · D. S. H. Chan · X. Y. Liu · R. Q. Han · D.-L. Kwong
    [Show abstract] [Hide abstract]
    ABSTRACT: Metal-oxide-semiconductor (MOS) devices using a thermally robust HfN/HfO2 gate stack were fabricated. The equivalent oxide thickness of HfN/HfO2 gate stack has been aggressively scaled down to 0.75 and 0.95 nm for MOS capacitors and metal-oxide-semiconductor field effect transistors, respectively, after a thermal budget required by the conventional complementary metal-oxide-semiconductor gate-first process. The reliability issues such as time-dependent dielectric breakdown (TDDB) and bias temperature instability (BTI) of the HfN/HfO2 devices are studied. The stress electric-field-dependent TDDB characteristics are demonstrated and explained by a model taking into account the high energetic carrier trapping in the HfO2 and at the HfO2/Si interfacial layer. The polarity dependent BTI characteristics are observed which can be explained by a generalized reaction-diffusion model. These intrinsic reliability characteristics are correlated with the low pre-existing charge traps in HfO2 gate stack resulting from a high temperature postdeposition annealing of the HfN/HfO2 gate stack. (c) 2007 The Electrochemical Society.
    Preview · Article · Nov 2007 · Journal of The Electrochemical Society

Publication Stats

2k Citations
224.76 Total Impact Points

Institutions

  • 2007-2009
    • National University of Singapore
      • Department of Electrical & Computer Engineering
      Singapore, Singapore
    • University of Texas at Austin
      • Department of Electrical & Computer Engineering
      Austin, Texas, United States
  • 2004-2005
    • Peking University
      • Institute of Microelectron
      Beijing, Beijing Shi, China