[Show abstract][Hide abstract] ABSTRACT: We completed the demonstration of three key functions of SOONO devices by demonstrating the DRAM characteristics of FD and PD SOONO devices successfully, together with the previously reported logic transistor and flash memory characteristics. Floating body SOONO DRAM cells implemented on electrically thin buried insulator shows the large sensing margins more than 5muA in FD device with long data retention and nondestructive read even at the W/L of 60/55nm which is the smallest IT DRAM ever reported.
[Show abstract][Hide abstract] ABSTRACT: We proposed and successfully demonstrated partially insulated and bulk MOSFETs with multiple V<sub>th</sub>s, I<sub>on</sub>s, and I<sub>Off</sub>s by using partial SOI process without complex process and SOI wafer. Both nMOS and pMOS applicable to the HP and LSTP transistors were simultaneously implemented on the same wafer with the same process except partial SOI process. These results must be very useful to implement IC systems requiring various specifications of V<sub>TH</sub>s, I<sub>On</sub>s, and I<sub>Off</sub>s.
[Show abstract][Hide abstract] ABSTRACT: We successfully demonstrate highly scaled damascene gate FinFET SONOS memory implemented on bulk silicon wafer. The FinFET SONOS devices show extremely high program/erase speed, large threshold voltage shifts over 4V at 1μs/12V for program and 50μs/-12V for erase, good retention time, and acceptable endurance. Thus, in sub-50nm regimes, ultra high speed operation becomes possible by using FinFET SONOS structure without sacrificing retention time.
[Show abstract][Hide abstract] ABSTRACT: In this paper, the hot carrier reliability of double gate (DG) MOSFETs is evaluated by simulations. The effect of floating body and volume inversion on hot carrier injection in DG is studied. It proves that thin body DG has good immunity to hot carrier injection into the gate electrodes. And for the application of DG in nonvolatile memory, an effective method is suggested to control the hot carrier injection in DG.
[Show abstract][Hide abstract] ABSTRACT: In this article, we evaluated the structural merits of a partially insulated MOSFET (PiFET), for ultimate scaling of planar MOSFETs, through simulation and fabrication. The newly fabricated PiFET showed outstanding short channel effect (SCE) immunity and off-current characteristics over the conventional MOSFET, resulting from a self-induced halo region, self-limiting S/D shallow junction, and reduced junction area due to PiOX layer formation. Thus, the PiFET can be an attractive alternative for ultimate scaling of planar MOSFETs.