[Show abstract][Hide abstract] ABSTRACT: A nanogap field-effect transistor with PCBM, a C60 derivative, is demonstrated, and evidence for nanogap filling is provided. The transistor serves as a charge-based detector to identify the imbibitions of the nanoscale capillary channel originating from the high-electron receptivity of the PCBM. In an extended application, a 2-bit-per-cell nonvolatile memory operation is performed, and the transistor is verified as a promising candidate without interference from adjacent memory cells.
[Show abstract][Hide abstract] ABSTRACT: We report the synthesis of free-standing MnSi nanowires via a vapor transport method with no catalyst and measurements of their electrical and magnetic properties for the first time. The single-crystalline MnSi nanowire ensemble with a simple cubic (B20) crystal structure shows itinerant helimagnetic properties with a T(c) of about 30 K. A single MnSi nanowire device was fabricated by a new method using photolithography and a nanomanipulator that produces good ohmic contacts. The single-nanowire device measurements provide large (20%) negative magnetoresistance and very low electrical resistivity of 544 microOmegacm for the MnSi nanowire.
[Show abstract][Hide abstract] ABSTRACT: Unified random access memory (URAM) with a separated double-gate is demonstrated on a fully depleted polysilicon (poly-Si) thin-film-transistor (TFT) template. Integration of a front-gate dielectric of tunneling oxide/nitride/control oxide (O/N/O) and a floating poly-Si channel provides the two versatile functions of nonvolatile silicon oxide-nitride oxide-semiconductor Flash memory and high-speed capacitorless single-transistor 1T-DRAM in a single transistor. In this design, the memory mode of URAM is selected according to user specifications. As the back-channel is assigned for capacitorless 1T-DRAM while the front-channel is devoted for Flash memory, spatial separation minimizes undesired soft programming in the front O/N/O layer and allows for capacitorless 1T-DRAM operation irrespective of the data state of the nonvolatile memory. This feature presents interference-free operation between the two modes. In addition, the virtue of the TFT process allows the potential for stackable memory for ultra-high-density era.
Preview · Article · Apr 2010 · IEEE Transactions on Electron Devices
[Show abstract][Hide abstract] ABSTRACT: With a simple and conformal metal nanocrystal dipping of synthesized micelles, nonvolatile
memory characteristics originating from a metallic cobalt (Co) core nanocrystal (NC)
surrounded by a Co-oxide shell are investigated in this study. From transmission electron
microscopy (TEM) and x-ray photoelectron spectroscopy (XPS), it was confirmed that
Co-oxide was made by oxygen plasma for polymer oxidation and that metallic Co wrapped
with a Co-oxide shell was made by hydrogen annealing in order to reduce the Co-oxide.
Energy band diagrams considering the extent of the coexistent metallic Co/Co-oxide were
also analyzed in terms of how they correspond to each program/erase/retention
case. These cases were verified by electrically measured data. These results can
provide a guideline for the design and optimization of metal NC embedded memory.
[Show abstract][Hide abstract] ABSTRACT: Gold nanoparticle (GN) embedded silicon nanowire (SiNW) configuration was proposed as a new biosensor for label-free DNA detection to enhance the sensitivity. The electric current flow between two terminals, a source and a drain electrode, were measured to sense the immobilization of probe oligonucleotides and their hybridization with target oligonucleotides. The complementary target oligonucleotide, breast cancer DNA with 1 pM, was sensed. In addition, its sensing mechanism and limit of detection (LOD) enhancement was investigated through simulation. The results support that the LOD can be improved by reducing the SiNW doping concentration. This emerging architecture combined nanostructure of spherical GN and SiNW has high potential as a label-free biosensor due to its facile fabrication process, high thermal stability, immobilization efficiency with a thiol-group in a self-assembled monolayer (SAM), and improved sensitivity.
Full-text · Article · Feb 2010 · Biosensors & Bioelectronics
[Show abstract][Hide abstract] ABSTRACT: A one-transistor nonvolatile SRAM (ONSRAM) on a silicon nanowire (SiNW) SONOS is demonstrated. A nonvolatile memory (NVM) property is attained by employment of O/N/O gate dielectric stacks as an electron storage node, and SRAM functionality is achieved by exploiting latch phenomena of a floating body in SiNW. Abrupt inverter switching, superior sensing current (Â¿21Â¿A), and robust interference immunity between SRAM and NVM verify the feasibility for the suggested ONSRAM.
[Show abstract][Hide abstract] ABSTRACT: The isolation-dielectric effects of a FinFET structure with a partially depleted (PD) silicon-on-insulator (PDSOI) region as a charge storage node on the characteristics of 1T-DRAM are reported in this brief. By introducing the low-permittivity isolation dielectric as an isolation layer among the active regions, the body potential over the PDSOI region is reduced due to the decreased capacitive coupling between the gate and the PD region; hence, it yields a widened 1T-DRAM sensing margin despite high off-state and low on-state currents. The increased gate height shows the high sensitivity of the sensing margin through the isolation-dielectric permittivity in the PDSOI FinFET 1T-DRAM.
Preview · Article · Jan 2010 · IEEE Transactions on Electron Devices
[Show abstract][Hide abstract] ABSTRACT: A capacitorless 1T-DRAM is fabricated on a fully depleted poly-Si thin-film transistor (TFT) template. A heavily doped back gate with a thin back-gate dielectric is employed to facilitate the formation of a deep potential well that retains excess holes. An asymmetric double gate (n<sup>+</sup> front gate and p<sup>+</sup> back gate) shows a wider sensing current window than a symmetric double gate (n<sup>+</sup> front gate and n<sup>+</sup> back gate). This is attributed to the inherent flatband voltage between the p<sup>+</sup> back gate and the channel inducing a deeper potential well, which allows capacitorless 1T-DRAM operation at a low back-gate voltage. The TFT capacitorless 1T-DRAM can be applied for future stackable memory for the ultrahigh density era.
Full-text · Article · Aug 2009 · IEEE Electron Device Letters
[Show abstract][Hide abstract] ABSTRACT: Keywords: Unified RAM (URAM) Multi-dual cell (MDC) Soft programming Background programming One-transistor (1T) capacitorless DRAM Non-volatile memory (NVM) a b s t r a c t New investigations are presented here on a high-density and DRAM-like high-speed non-volatile mem-ory (NVM) application of unified RAM (URAM). For a high-density application of URAM, multiple data storage is demonstrated with a multi-dual cell (MDC). Because each NVM state can be split by program-ming with a one-transistor (1T) DRAM without a capacitor, the total number of memory states can be doubled. Furthermore, a high-speed DRAM-level NVM scheme is proposed for the joint operation of 1T DRAM buffer programming and NVM post-background programming. The MDC and the proposed scheme are unique URAM properties that can extend the application range of memory devices.
Preview · Article · Aug 2009 · Microelectronic Engineering
[Show abstract][Hide abstract] ABSTRACT: A band-offset-based unified-RAM (URAM) cell fabricated on a Si/Si<sub>1-y</sub>C<sub>y</sub> substrate is presented for the fusion of a nonvolatile memory (NVM) and a capacitorless 1T-DRAM. An oxide/nitride/oxide (O/N/O) gate dielectric and a floating-body are combined in a FinFET structure to perform URAM operation in a single transistor. The O/N/O layer is utilized as a charge trap layer for NVM, and the floating-body is used as an excess hole storage node for capacitorless 1T-DRAM. The introduction of a pseudomorphic SiC-based heteroepitaxial layer into the Si substrate provides band offset in a valence band. The FinFET fabricated on the energy-band-engineered Si<sub>1-y</sub>C<sub>y</sub> substrate allows hole accumulation in the channel for 1T-DRAM. The band-engineered URAM yields a cost-effective process that is compatible with a conventional body-tied FinFET SONOS. The fabricated URAM shows highly reliable NVM and high-speed 1T-DRAM operations in a single memory cell.
Full-text · Article · May 2009 · IEEE Transactions on Electron Devices
[Show abstract][Hide abstract] ABSTRACT: This paper investigates how gate height (H<sub>g</sub>), which refers to the size of a floating-body, affects the program efficiency and retention characteristics of one-transistor DRAM (1T-DRAM) and nonvolatile memory (NVM) for a FinFET SONOS device that has a partially depleted silicon-on-insulator (PDSOI) region as a charge storage node for a 1T-DRAM operation. A device with a lower H<sub>g</sub> yields enhanced program efficiency due to the higher impact ionization rate caused by the enlarged PDSOI region for both 1T-DRAM and NVM operations. The device with the lower H<sub>g</sub> shows slightly poor retention characteristics in the NVM unlike the 1T-DRAM.
Full-text · Article · May 2009 · IEEE Transactions on Electron Devices
[Show abstract][Hide abstract] ABSTRACT: The review of this paper was arranged by Prof. A. Zaslavsky Keywords: Nonvolatile memories (NVM) Nanocrystal (NC) Geometric effect Block copolymer (BCP) nanotemplate Modeling Capacitive-coupling ratio a b s t r a c t This study describes geometric characteristics of a nonvolatile memory (NVM) device with a designed chromium (Cr) nanocrystal (NC) floating gate. By using a block copolymer (BCP) nanotemplate as a mask layer, cone-shaped NCs and disc-shaped NCs were formed. It was found that the NVM device using the cone-shaped NC had a better program efficiency than that of the device using the disc-shaped one. This trend was verified by a theoretical model, which considered an effect of the capacitive-coupling ratio between a control gate and a NC floating gate.
[Show abstract][Hide abstract] ABSTRACT: A double-stacked nanocrystal (DSNC) flash memory is presented for improvement of both program/erase (P/E) speed and data retention time. Four combinations of nickel (Ni) and gold (Au) (Ni/Ni, Au/Au, Ni/Au, and Au/Ni) are used as charge storage DSNC materials and are compared from the perspective of memory performance. Through experimental results for P/E efficiency and retention time, the optimized energy band lineup for faster P/E and longer charge retention is presented. A combination of a deep potential well at the top and a shallow potential well at the bottom exhibits optimized performance in P/E, and this combination also shows the longest data retention characteristics.
Full-text · Article · Apr 2009 · IEEE Transactions on Electron Devices
[Show abstract][Hide abstract] ABSTRACT: This paper describes a unified memory (URAM) that utilizes a nanocrystal SOI MOSFET for multi-functional applications of both nonvolatile memory (NVM) and capacitorless 1T-DRAM. By using a discrete storage node (Ag nanocrystal) as the floating gate of the NVM, high defect immunity and 2-bit/cell operation were achieved. The embedded nanocrystal NVM also showed 1T-DRAM operation (program/erase time=100ns) characteristics, which were realized by storing holes in the floating body of the SOI MOSFET, without requiring an external capacitor. Three-bit/cell operation was accomplished for different applications – 2-bits for nonvolatility and 1-bit for fast operation.
Full-text · Article · Mar 2009 · Solid-State Electronics
[Show abstract][Hide abstract] ABSTRACT: A soft-programming-free operation method in unified RAM (URAM) is presented. An oxide/nitride/oxide (O/N/O) layer and a floating-body are integrated in a FinFET, thereby providing the versatile functions of a high-speed capacitorless 1T-DRAM, as well as nonvolatile memory, and the mode of the memory cell can be selected and independently utilized according to the designer's demand. With the utilization of the impact ionization method for 1T-DRAM programming, undesired soft charge trapping into O/N/O gradually shifts the threshold voltage, resulting in an unstable operation in the URAM. In order to avoid such problems associated with soft programming, a gate-induced drain-leakage (GIDL) program method is proposed for improved immunity to disturbance. It is found that the GIDL method effectively suppresses soft programming without sacrificing the sensing current window.
Preview · Article · Mar 2009 · IEEE Electron Device Letters
[Show abstract][Hide abstract] ABSTRACT: A novel fusion memory is proposed as a new paradigm of silicon based memory technology. An O/N/O gate dielectric and a floating body are combined with a FinFET, and the non-volatile memory (NVM) and high speed capacitorless 1T-DRAM are performed in a single transistor. A nitride trap layer is used as an electron storage node for NVM, and hetero-epitaxially grown Si/Si<sub>1-x</sub>Ge<sub>x</sub> energy band engineered bulk substrates allow excess hole storage for 1T-DRAM. Highly reliable 1T-DRAM and NVM are demonstrated.
[Show abstract][Hide abstract] ABSTRACT: A nonvolatile memory is demonstrated using a solution-processed sol-gel ZnO thin-film transistor (TFT) in which Ag nanoparticles are embedded as charge storage nodes at the insulator-ZnO interface. Its TFT transfer characteristics exhibit a large clockwise hysteresis that is proportional to the gate bias sweep range. Measurement of the threshold voltage shift versus the pulse width of gate bias reveals that the device can be programed or erased at a time scale of as short as 10−4 s. Retention of the initial memory window is measured to be 27% after 105 s and projected to last until 107 s.
Preview · Article · Dec 2008 · Applied Physics Letters
[Show abstract][Hide abstract] ABSTRACT: Metal nanocrystals synthesized with a micellar template were applied for three-dimensional vertical floating gate memory devices. Using a highly ordered micellar template formed with a diblock copolymer, we produced cobalt (Co) nanocrystals with a uniform size and spatial distribution on a planar surface and a sidewall surface. The hydrogen annealing effects were investigated in terms of memory performance. The fabricated vertical floating gate memory with Co nanocrystals annealed with hydrogen showed a memory window with a voltage greater than 1 V and a retention time characteristic that preserves more than 60% of the initial charge after ten years.
[Show abstract][Hide abstract] ABSTRACT: Unified random access memory (URAM) is demonstrated for the first time. The novel partially depleted (PD) SONOS FinFET provides unified function of a high-speed capacitorless 1T DRAM and a nonvolatile memory (NVM). The combination of an oxide/nitride/oxide (O/N/O) layer and a floating-body facilitates URAM operation in PD SONOS FinFETs. An NVM function is achieved by FN tunneling into the O/N/O stack and, a 1T-DRAM function is achieved by excessive-hole accumulation in the PD body. The fabricated PD SONOS FinFET shows retention time exceeding 10 years for NVM operation and program/erase time below 6 ns for 1T-DRAM in a single-cell transistor. These two memory functions are guaranteed without disturbance between them.
Full-text · Article · Aug 2008 · IEEE Electron Device Letters
[Show abstract][Hide abstract] ABSTRACT: A FinFET-based unified-RAM (URAM) using the band offset of Si/SiC is demonstrated for the fusion of a non-volatile memory (NVM) and capacitorless 1T-DRAM operation. An oxide/nitride/oxide (O/N/O) gate dielectric and a floating body caused by the band offset are combined in a bulk FinFET to allow two memory operations in a single transistor. The device is fabricated on an epitaxially grown Si/SiC substrate and its process is fully compatible with a conventional bulk FinFET SONOS. Highly reliable NVM and high speed 1T-DRAM operation are confirmed in a single URAM cell.