- [Show abstract] [Hide abstract] ABSTRACT: In this paper, the volume trap densities Nt are extracted from gate-all-around silicone-nanowire FETs with different gate oxides, using a cylindrical-coordinate-based flicker noise model developed. For extracting Nt , the drain-current power spectral densities were measured from a large number of identical devices and averaged over, thereby mimicking the spatial distribution of trap sites inducing 1/ f curve. Also, effective mobility and threshold voltage were simultaneously extracted with the series resistance to characterize the 1/ f noise in terms of intrinsic values of these two channel parameters. The volume trap densities thus extracted from different oxides (in situ steam-generated oxide/rapid thermal oxide/nitride-gated oxide) are compared and further examined using hot-carrier stress data. Finally, radius dependence of the cylindrical 1/ f model developed is discussed.
- [Show abstract] [Hide abstract] ABSTRACT: Presented in this letter are the C - V data, measured from nanowire capacitors, which have been fabricated by connecting in parallel a large number of identically processed nanowire FETs. The C - V curves were examined over a range from accumulation to inversion with varying frequencies and at different electrode configurations. The gate response of the undoped and floating channel is investigated using C - V data, and the inversion charge and carrier mobility are accurately extracted by eliminating the effects of parasitic capacitances and series resistance R <sub>sd</sub>. These observed data are compared with the data from planar MOS capacitor.
- [Show abstract] [Hide abstract] ABSTRACT: In this paper, we introduce the cylindrical coordinate based flicker noise model for Silicon NanoWire Field Effect Transistor (Si-NWFET) with Gate-All-Around (GAA) structure. For the accurate extraction of the volume trap density, N<sub>t</sub>, with 1/f noise modeling, the parameters which represent the intrinsic channel properties are determined by rejecting the series resistance R<sub>sd</sub> effect. Due to the random distribution of traps in Si-NWFETs, the 1/f noise data are obtained by averaging the drain current power spectral density, S<sub>id</sub>, for several devices. By using the proposed 1/f model, the extracted volume trap density is compared for three different oxide processes (ISSG/RTO/GNOx) and verified by hot carrier stress test.
- [Show abstract] [Hide abstract] ABSTRACT: We have proposed gate-all-around Silicon nanowire MOSFET (SNWFET) on bulk Si as an ultimate transistor. Well controlled processes are used to achieve gate length (LG) of sub-10nm and narrow nanowire widths. Excellent performance with reasonable VTH and short channel immunity are achieved owing to thin nanowire channel, self-aligned gate, and GAA structure. Transistor performance with gate length of 10nm has been demonstrated and nanowire size (DNW) dependency of various electrical characteristics has been investigated. Random telegraph noise (RTN) in SNWFET is studied as well.
- [Show abstract] [Hide abstract] ABSTRACT: The series resistance Rsd and the electron and hole mobilities, extracted from n- and p-type Si-nanowire field effect transitors (Si-NWFETs) using the Y-function technique are compared. Both n- and p-NWFETs show similar Rsd values but n-NWFETs have larger Rsd variation from device to device than p-NWFETs. Also, compared with n-NWFETs, p-NWFETs exhibit higher low-field mobility μ0 but severe mobility degradation, regardless of channel length in the high gate voltage Vgs region. With decreasing channel length and increasing lateral electric field for a given drain voltage, n-NWFETs exhibit low-field mobility (μ0) degradation resulting from the velocity saturation. In contrast, the hole mobility in p-NWFETs remains nearly constant and is consistant with its larger critical electric field, Ec.
- [Show abstract] [Hide abstract] ABSTRACT: The series resistance, R <sub>sd</sub> in silicon nanowire FETs (Si-NWFET) is extracted unambiguously, using the Y -function technique, in conjunction with the drain current and transconductance data. The volume channel inversion in Si-NWFET renders the charge carriers relatively free of the surface scattering and concomitant degradation of mobility. As a result, the Y -function of Si-NWFET is shown to exhibit a linear behavior in strong inversion, thereby enabling accurate extraction of R <sub>sd</sub>. The technique is applied to nanowire devices with channel lengths 82, 86, 96, 106, 132, and 164 nm, respectively. The extracted R <sub>sd</sub> values are shown nearly flat with respect to the gate voltage, as expected from Ohmic contacts but showed a large variation for all channel lengths examined. This indicates the process parameters involved in the formation of series contacts vary considerably from device to device. The present method only requires a single device for extraction of R <sub>sd</sub> and the iteration procedure for data fitting is fast and stable.
- [Show abstract] [Hide abstract] ABSTRACT: Temperature-dependent electrical transport measurements of cylindrical shaped gate-all-around silicon nanowire p-channel MOSFET were performed. At 4.2 K, they show current oscillations, which can be analyzed by single hole tunneling originated from nanowire quantum dots. In addition to this single hole tunneling, one device exhibited strong current peaks, surviving even at room temperature. The separations between these current peaks corresponded to the energy of 25 and 26 meV. These values were consistent with the sum of the bound-state energy spacing and the charging energy of a single boron atom. The radius calculated from the obtained single-atom charging energy was also comparable to the light-hole Bohr radius.
Conference Paper: Sub-10 nm Gate-All-Around CMOS Nanowire Transistors on Bulk Si Substrate[Show abstract] [Hide abstract] ABSTRACT: In this paper, sub-10 nm gate-all-around (GAA) CMOS silicon nanowire field-effect transistors (SNWFET) on bulk Si substrate are fabricated successfully for the first time with 13-nm-diameter silicon nanowire channel. On-state currents of 1494/1054 muA/mum at off leakage currents of 102/6.44 nA/mum are obtained for N/PMOS, respectively. The impacts of nanowire diameter (D<sub>NW</sub>) and gate oxide thickness (T<sub>OX</sub>) as well S/D parasitic resistance (R<sub>SD</sub>) on performance are investigated in details.
- [Show abstract] [Hide abstract] ABSTRACT: Sub 5 nm tri-gate nanowire MOSFET is successfully developed with good uniformity by using conventional technology in the SOI structure. Performance of the poly Si channel is compared with that of the single Si channel. On-state current of n-FET has attained to 802 uA/um for single Si channel, while 471 uA/um for poly Si channel, which is 60 % of performance of the single Si channel at L<sub>G</sub> ~ 5 nm due to the enhancement of ballistic efficiency. At the extremely small L<sub>G</sub> of around 5 nm, we also investigate off-leakage current with boosted BJT operation.
- [Show abstract] [Hide abstract] ABSTRACT: Hot carrier (HC) reliability of gate-all-around twin Si nanowire field effect transistor (GAA TSNWFET) is reported and discussed with respect to size and shape of nanowire channel, gate length, thickness and kind of gate dielectric in detail. Smaller nanowire channel size, shorter gate length and thinner gate oxide down to 2 nm thickness show worse hot carrier reliability. The worst V<sub>D</sub> for 10 years guaranty, 1.31 V, satisfies requirement of ITRS roadmap.
- [Show abstract] [Hide abstract] ABSTRACT: In this work, fabrication of TSNWFET on SOI with down to 25-nm TiN surrounding gate and 8-nm silicon nanowires is reported with high manufacturability and improved device reliability including reduced junction and gate leakage currents by fully eliminating the bottom parasitic channel existing in previous TSNWFET on bulk Si. And high performance is also obtained to be 1124muA/mum and 1468muA/mum at off current of 1nA/mum for NMOS and PMOS, respectively.
- [Show abstract] [Hide abstract] ABSTRACT: I<sub>ON</sub> is increased about 25 % with the width/height (W/H) of 12/24 nm nanowire (NW) in comparison with the W/H of 12/12 nm at V<sub>G</sub>-V<sub>TH</sub> = 1 V. With these results, we have successfully fabricated NW SRAM arrays with the W/H of 5/15 nm and LG of 40 nm for the first time. Static noise margin (SNM) of 325 mV is achieved at V<sub>D</sub> = 1 V. NW height and gate oxide thickness dependency of n-ch twin silicon nanowire MOSFET (TSNWFET) on device variations is investigated. Line edge roughness and size variation are more critical than random dopant fluctuation in TSNWFET.
- [Show abstract] [Hide abstract] ABSTRACT: Temperature (T) dependent transport measurements of cylindrical shaped gate-all-around silicon nanowire MOSFETs (SNWFETs) were performed. Single electron tunneling behaviors were observed at 4.2 K and one of the devices exhibited anomalously strong current peak which survived even at room temperature. The observed peak was interpreted as an evidence of transport through single impurities in the channel.
- [Show abstract] [Hide abstract] ABSTRACT: A gate-all-around (GAA) twin silicon nanowire MOSFET (TSNWFET) with 5-nm-radius channels on a bulk Si wafer is successfully fabricated to achieve extremely high-drive currents of 2.37 mA/ mum for n-channel and 1.30 mA/ mum for p-channel TSNWFETs with mid-gap TiN metal gate that are normalized by a nanowire diameter. It also shows good short-channel effects immunity down to 30-nm gate length due to the GAA structure and the nanowire channel. The effect of bottom parasitic transistor in TSNWFET is also investigated.
- [Show abstract] [Hide abstract] ABSTRACT: We have investigated the electrical characteristics of cylindrical gate-all-around twin silicon nanowire metal-oxide-semiconductor field effect-transistors with 4 nm radius and the gate length ranging from 22 to 408 nm. We observed strong transconductance overshoot in the linear source-drain bias regime in the devices with channel length shorter than 46 nm. The mean free path estimated from the slope of the zero-field one dimensional ballistic resistance measured as a function of device length was almost the same as this length. (c) 2008 American Institute of Physics.
Conference Paper: Investigation of nanowire size dependency on TSNWFET[Show abstract] [Hide abstract] ABSTRACT: Nanowire size (dNW) dependency of various electrical characteristics on gate all around twin silicon nanowire MOSFET (TSNWFET) is investigated to understand overall performance of nanowire transistor deeply. When dNW decreases, current drivability (Ion) normalized by circumference at the same VG-VTH improves and maximizes at dNW of 4 nm. And mobility is also estimated with capacitance and series resistance. All the experimental investigation shows that dNW of 4 nm is the best point to maximize the volume inversion effect on gate all around nanowire MOSFET.
- [Show abstract] [Hide abstract] ABSTRACT: Strained silicon nanowire transistor with embedded SiGe (e-SG) source/drain is investigated for the first time on experiments. By compressive stress induced by e-SG, PMOS performance is improved by about 85%. <110>-oriented nanowire channel also contributes 80% PMOS performance improvement relative to <100> direction. By combination of uniaxial stress and <110> channel direction, up to 136% PMOS performance enhancement is obtained so that superior PMOSFET to NMOSFET is for the first time observed with silicon channel material.
- [Show abstract] [Hide abstract] ABSTRACT: The characteristics of cylindrical gate-all-around twin silicon nanowire field-effect transistors with a radius of 5 nm have been measured in temperatures T ranging from 4 to 300 K. The dependence of the off-current suggests that thermal generation in the channel is the main leakage mechanism. The dependence of the subthreshold swing exhibits no body effects but shows degradations due to slight differences in the threshold voltages and in the body effect constants of the twin nanowires. The T dependence of the peak normalized transconductance g<sub>m</sub> /V<sub>DS</sub> gives a clue of 1-D phonon scattering and suggests that surface roughness scattering at the nanowire wall is dominant at low values.
Sŏul, Seoul, South Korea
- Department of Electrical Engineering