[Show abstract][Hide abstract] ABSTRACT: This paper presents a capacitor-less 1T DRAM cell transistor with high scalability and long retention time. It adopts gate to source/drain non-overlap structure to suppress junction leakage, which results in 80 ms retention time at 85degC with gate length of 55 nm. Compared to the previous reports, proposed cell transistor shows twice longer retention time even though the gate length shrinks to the half of them. By TCAD analysis, we have confirmed that the improvements are attributed to the superiority of the proposed device structure.
[Show abstract][Hide abstract] ABSTRACT: Ultra Thin Body Si-On-ONO (UTB SOONO) transistors with ultra thin spacer are successfully demonstrated and evaluated. They have shown increased driving current more than 30% compared with conventional UTB SOONO transistors with thick spacer due to reduced source/drain resistance without short channel effect degradation by using thin spacer. In this paper, it is shown that thin spacer technology is very attractive to UTB SOI device in terms of device performance and process simplicity.
[Show abstract][Hide abstract] ABSTRACT: As DRAM cell pitch size scales, the DRAM cells have required characteristics of high performance transistors. In this paper, we proposed and successfully demonstrated high performance silicon-on-ONO (SOONO) cell array transistors (SCATs) for 512Mb DRAM cell array application. They have advantages of SOI substrate and 3-D hi-gate as well as process simplicity. From those advantages, they have low Ioff due to good SCE immunity with DIBL of 40 mV/V and SS of 84 mV/dec, low GIDL current, low junction leakage current, and low junction capacitance as well as no body bias dependence. Thus, the SCATs may be a promising solution satisfying the requirements of DRAM cells with scaling.
[Show abstract][Hide abstract] ABSTRACT: In this study, we compared sensing margin according to the back gate bias and body doping concentration. We achieved large sensing margin of 62 uA/um at L<sub>G</sub> = 87 run and demonstrated sensing margin of 45 uA/um with L<sub>G</sub> = 47 nm that is the smallest device ever reported for the floating body RAM. For the scaling down to the sub 50 nm gate length, we should reduce the body thickness for the SCE with optimum body doping condition . Possibility of scaling down with the capacitor-less RAM is shown to the sub 50 nm from this result.
[Show abstract][Hide abstract] ABSTRACT: We completed the demonstration of three key functions of SOONO devices by demonstrating the DRAM characteristics of FD and PD SOONO devices successfully, together with the previously reported logic transistor and flash memory characteristics. Floating body SOONO DRAM cells implemented on electrically thin buried insulator shows the large sensing margins more than 5muA in FD device with long data retention and nondestructive read even at the W/L of 60/55nm which is the smallest IT DRAM ever reported.
[Show abstract][Hide abstract] ABSTRACT: In this article, we report improved results of 4-bit double SONOS memories (DSMs) with 4-storage nodes through the optimization of ONO layer thicknesses for front and back sides. They show more balanced characteristics between the front and back channels, higher V<sub>TH </sub> shifts above 2.4V, larger read margins above 1.6V, better endurance, and longer retention time than our previous results. In addition, we also propose and demonstrate a highly scaled 4-bit DSM using multi-level technology. The V<sub>TH</sub> shifts above 4V splitting into 4 levels without noticeable interferences are achieved. Each nodes show clear 4 levels with good retention
[Show abstract][Hide abstract] ABSTRACT: As planar MOSFETs are scaled down, it is more and more difficult to achieve the scaled transistors with high performance. One of the key issues must be large source/drain (S/D) resistance as well as short channel effects (SCEs) (Ghani et al., 2001). These are in trade-off relation because shallow junction for reducing SCEs causes the increase of S/D resistance. One of the solutions to solve both problems may be elevated S/D technique. However, it seems to be another burden in consideration of growing the epitaxial layers on thin body (Widodo et al., 2005). Another solution is to reduce the spacer thickness (Yang et al., 2003). Through this approach, we can reduce the S/D resistance without any sacrifice of short channel effect (SCE) immunity. The requirements of spacer thickness and parasitic S/D resistance along technology node are shown in this paper. Recently, we proposed and successfully demonstrated partially insulated MOSFETs (PiFETs) as an alternative of ultra thin body (UTB) SOI devices (Kim et al., 2005). These are free from floating body, heat dissipation and high cost in comparison with conventional UTB SOI transistors. Despite of these merits, PiFETs like UTB SOI devices still suffer from large S/D resistance as their gate length are scaled down. In this paper, we evaluate characteristics of bulk MOSFETs with ultra thin spacer (UTS) and demonstrate the improved performance of 16 nm UTS PUC MOSFETs among PiFETs due to reduced S/D resistance
[Show abstract][Hide abstract] ABSTRACT: We proposed and successfully demonstrated Si-on-ONO (SOONO) devices for fully depleted SOI transistor and 4 bit flash memory applications. In terms of HP transistor, SOONO MOSFETs showed good SCE immunity and high driving currents. In terms of a 4-bit flash memory, SOONO MOSFETs with ONO layers as their gate dielectrics showed clear 4-bit operation using the physically separated 4 storage nodes of double ONO layers
[Show abstract][Hide abstract] ABSTRACT: We proposed and successfully demonstrate multi-functional Si-on-ONO (SOONO) MOSFETs. As a high performance transistor and embedded 2-bit flash memory, they show the reasonable characteristics. SOONO MOSFETs act as ultra thin body transistor with self-limited shallow junction, resulting in good SCE immunity and high driving currents, 737muA/mum for nMOS and 330muA/mum for pMOS at |V<sub>GS</sub>| = |V<sub>DS</sub>| = 1 V, I<sub>OFF</sub> = 100 nA/mum). In terms of flash memory, SOONO MOSFET acts as 2-bit flash memory with 2 physically separated storage node in back side. By using CHEI/HHI program/erase, each node was easily programmed and erased. In the gate length of 120 nm, we achieved the read/write margins of ~1.3 V at V<sub>DS</sub> = 1.2 V and the V<sub>TH</sub> shifts of ~2.5V for both program/erase
[Show abstract][Hide abstract] ABSTRACT: For the first time, titanium-nitride (TiN) single metal gate and high-k hafnium-silicate (HfSiO<sub>x</sub>) gate dielectric have been successfully integrated in 55nm McFET SRAM cell. The use of HfSiO<sub>x </sub> gate dielectric, not only reduces gate leakage current but also improves I<sub>ON</sub>/I<sub>OFF</sub> ratio of PFET to 10<sup>8</sup>. Using local fin implantation (LFI) scheme, junction capacitance is reduced by 13% and junction breakdown voltage is increased by 1.4V
[Show abstract][Hide abstract] ABSTRACT: We proposed a 4-bit double SONOS memory with two ONO layers, 4 storage nodes, for ultimate multi-bit operation and firstly demonstrate 4-bit operation using the physically separated 4 storage nodes. By using CHEI/HHI program/erase, each node was easily programmed and erased without any detrimental interference among the nodes. In the gate length of 120nm, the read/write margins of ~0.8V for front side (FS) and ~1.1V for back side (BS) at V<sub>DS</sub>=1.2V was obtained. The V<sub>TH </sub> shifts of ~1.5V for both program/erase (P/E) were observed with the P/E conditions, V<sub>D</sub>/V<sub>FG</sub>=3/5V, 3/-4V for FS and VD/VBG=3.2/7V, 3.2/-5V for BS, respectively, with the duration of 1 ms. The V<sub>TH</sub> windows of ~0.9V for FS and ~1.1V for BS were achieved even after 10<sup>4</sup> P/E cycles
[Show abstract][Hide abstract] ABSTRACT: In this article, we proposed and successfully demonstrated 25 nm TiN metal gate nanorod transistors with laterally and vertically scaled actives without process burdens. They showed the excellent short channel effect immunity and high current drivability DIBLs are below 40 mV/V and subthreshold swings are nearly ideal values showing no temperature dependency. The driving currents of 1.4 mA/mum for nMOS and 1.0 mA/mum for pMOS are achieved at Ioff=100 nA/mum and VD =1.0 V. Thus, it is proven that laterally and vertically scaled nanorod transistors can be a promising solution for ultimate scaling