Yannis Tsividis

Columbia University, New York, New York, United States

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Publications (125)168.38 Total impact

  • Christos Vezyrtzis · Yannis Tsividis · Steven M. Nowick
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    ABSTRACT: A calibrated delay line is a key component in many modern digital systems. Traditionally, these lines are designed as real-time pipelines with static granularity, fine enough to handle a worst case input rate. However, due to their rigid structure, they have suboptimal energy for low- and varying-rate input streams. We introduce a complete methodology for designing reconfigurable delay lines that dynamically adapt their granularity to actual input traffic, on-the-fly, without stalling or disturbing normal operation. Two or more modes can be used, with different granularities to handle different traffic densities. During sparser traffic, the system is reconfigured to the proper coarser-grain mode, thereby reducing total energy, and it reverts to fine-grain mode during denser traffic. In each case, overall delay is preserved. This strategy is especially beneficial for applications where input traffic is highly varied. The particular focus of this paper is one promising domain, continuous-time digital signal processors (CT DSPs), a new class of processors targeting low-energy applications. The proposed system includes two lightweight asynchronous control blocks: a digital controller to continuously monitor input traffic, and a micropipeline to dynamically reconfigure the entire delay line. Design approaches for bimodal and trimodal adaptive lines are presented, which are then implemented in a 0.13- IBM CMOS technology. Simulations for these delay lines demonstrate savings in overall dynamic power up to 45.5% and 71.1%, respectively, when compared with a nonadaptive design, with only minimal area overhead (1.5% and 3%, respectively, for a targeted configuration). Using extensions to more configuration modes, further power reductions can be achieved. While results are presented for CT DSPs, significant benefits are also expected in many other domains, w- ere the delay lines are used.
    No preview · Article · Oct 2015 · IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • Pablo Martinez-Nuevo · Sharvil Patil · Yannis Tsividis
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    ABSTRACT: A new continuous-time level-crossing sampling LCS technique, which is called derivative LCS (DLCS), and associated reconstruction are proposed for bandpass signals. The derivative of the input is level-crossing sampled, and the result is transmitted; at the receiver, these samples are zero-order held and integrated, automatically resulting in piecewise-linear reconstruction, which has much lower quantization error than zero-order-hold (ZOH) reconstruction. Two refinements are presented, namely companded DLCS and adaptive-resolution DLCS. For some signals, the schemes proposed can significantly reduce the number of samples generated per unit of time, compared to schemes based on ZOH reconstruction, for a given signal-to-error ratio (SER), without the need for elaborate reconstruction techniques, such as linear prediction. Contrary to Nyquist-rate-clocked systems, DLCS and its variants exploit the varying spectral context and sparse structure of bursty signals by generating samples only when the signal rate of change requires it, thus promising to lead to low dynamic power dissipation in the associated hardware. Simulation results are presented.
    No preview · Article · Jan 2015 · Circuits and Systems II: Express Briefs, IEEE Transactions on
  • Christos Vezyrtzis · Weiwei Jiang · S.M. Nowick · Yannis Tsividis
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    ABSTRACT: This paper presents a clockless digital filter able to process inputs of different rates and formats, synchronous or asynchronous, with no adjustment needed to handle each input type. The filter is designed using a mix of asynchronous and real-time digital hardware, and for this reason relies on neither a clock nor the input data rate for setting its frequency response. The modular architecture of the filter, including delay segments with separated data and timing paths and a pipelined multi-way adder, allows easy extensions for different data widths. The filter was used as part of an ADC/DSP/DAC system which maintains its frequency response intact for varying sample rates without requiring any internal change. This property is not possible for any synchronous DSP system. The 16-tap, 8-bit FIR filter, integrated in a 130 nm CMOS process, includes on-chip automatic delay tuning, and for certain inputs, has signal-to-error ratio which exceeds that of clocked systems.
    No preview · Article · Oct 2014 · IEEE Journal of Solid-State Circuits
  • Yannis Tsividis
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    ABSTRACT: I grew up in a suburb near Athens, Greece, to a middle-class family that went through very difficult times. One of my earliest memories is of an attraction to musical instruments, especially pianos, and of my parents pulling me away from them; I was later told that they were afraid I would become a musician, and that I "would starve". To this day, I regret not having learned to play an instrument well. Yet music is very much a part of my life. I credit it, in part, for my interest in radio and audio and, through those, in all things electronic.
    No preview · Article · Sep 2014 · IEEE Solid-State Circuits Magazine
  • Yannis Tsividis
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    ABSTRACT: One often reads of cases in which the confluence of several factors, key among them the presence of a core of driven individuals, attracts other motivated people and leads to a happy situation characterized by enthusiasm and creativity, where ?sparks fly?. Examples can be found in many fields, from physics (e.g., University of G?ttingen, Germany, in the 1920s) to music (e.g., Louisville Orchestra, 1950s). In engineering, one of the best examples of this can be found in the Integrated Circuits Lab at the University of California, Berkeley, in the early-to-mid-70s and beyond.
    No preview · Article · Jan 2014 · IEEE Solid-State Circuits Magazine
  • Source
    Yannis Tsividis · John Milios
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    ABSTRACT: This paper discusses equivalent-circuit modeling of the electrochemical impedance corresponding to one-dimensional diffusion in a uniform medium. It argues that, of the several equivalent circuits in use for such modeling, one – namely the nonuniform resistance–capacitance ladder – has attractive properties that are not shared by any other equivalent circuit. Explicit, analytical expressions are derived for the efficient development of this ladder equivalent, which provide advantages compared to computer optimization. Although the context of this work is battery modeling, the results presented can be of value in other fields where diffusion is studied and modeled.
    Preview · Article · Oct 2013 · Journal of electroanalytical chemistry
  • Colin Weltin-Wu · Yannis Tsividis
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    ABSTRACT: This paper presents a clock-less 8b ADC in 130 nm CMOS technology, which uses signal-dependent sampling rate and adaptive resolution through a time-varying comparison window, for applications with sparse input signals. Input-dependent dynamic bias is used to reduce comparator delay dispersion, thus helping to maintain SNDR while saving power. Alias-free operation with SNDR in the range of 47-54 dB, which partly exceeds the theoretical limit of 8b conventional converters, is achieved over a 20 kHz bandwidth with 3-9 μW power from a 0.8 V supply.
    No preview · Article · Sep 2013 · IEEE Journal of Solid-State Circuits
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    ABSTRACT: Presented is a clockless, continuous-time (CT) GHz processor that bypasses some of the limitations of conventional digital and analog implementations. Per-edge digital signal encoding is used for parallel processing of continuous-time samples with a temporal spacing as narrow as 15 ps, generated by a 3-b CT flash ADC. Parallel digital delay chains and programmable charge pumps realize the asynchronous filtering operation, each consuming negligible power while awaiting a new sample. A six-tap CT ADC and CT digital FIR processor system occupies 0.07 mm2 and achieves dynamic range of over 20 dB in the 0.8-3.2-GHz signal range. The system's rate of operations automatically adapts to the signal, thus causing its power dissipation to vary in the range of 1.1 to 10 mW according to input activity.
    No preview · Article · Sep 2012 · IEEE Journal of Solid-State Circuits
  • Christos Vezyrtzis · Yannis Tsividis · Steven M. Nowick
    [Show abstract] [Hide abstract]
    ABSTRACT: A calibrated delay line is a key component in many modern digital systems. Traditionally, these lines are designed as real-time pipelines with static granularity, fine enough to handle a worst-case input rate. However, due to their rigid structure, they have sub-optimal energy for low- and varying-rate input streams. We introduce a complete methodology for designing reconfigurable delay lines which dynamically adapt granularity to traffic, on-the-fly, without stalling or disturbing normal operation. These lines have two modes: coarse- and fine-grain. During sparser traffic, the system is reconfigured to coarse-grain mode, thereby reducing total energy, and it reverts to fine-grain mode during denser traffic. In each case, overall delay is preserved. This strategy is especially beneficial for applications where input traffic is highly varied. The particular focus of this paper is on one promising domain, continuous-time digital signal processors (CT DSP's), a new class of processors targeting low-energy applications. The proposed system includes two lightweight asynchronous control blocks: a digital controller to continuously monitor input traffic, and a micropipeline to dynamically reconfigure the entire delay line. With a complete implementation in a 0.13 um IBM CMOS technology, post-layout simulations demonstrate an average overall dynamic power reduction up to 45.5% compared to a non-adaptive design, with only minimal area overhead. The design methodology is modular, supporting extensions to multiple configuration modes to provide even greater power reduction for a variety of input traffic. While results are presented for CT DSP's, significant benefits are also expected in many other domains where delay lines are used.
    No preview · Conference Paper · Sep 2012
  • Tao Mai · Yannis Tsividis
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    ABSTRACT: We convert linear continuous-time systems based on delays to internally nonlinear ones, with unchanged input–output behavior. The internal nonlinearities can be chosen so that the internal modified noise transfer functions result in improved output signal-to-noise ratio for small inputs, thus extending the usable dynamic range. This results in companding signal processors, of which two examples are given—one using syllabic and one using instantaneous companding. This study complements earlier work on externally linear continuous-time systems with rational transfer functions and on such systems containing discrete-time delays.
    No preview · Article · Aug 2012 · Circuits and Systems II: Express Briefs, IEEE Transactions on
  • Simha Sethumadhavan · Ryan Roberts · Yannis Tsividis
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    ABSTRACT: Current technology trends indicate that power- and energyefficiency will limit chip throughput in the future. Current solutions to these problems, either in the way of programmable or fixed-function digital accelerators will soon reach their limits as microarchitectural overheads are successively trimmed. A significant departure from current computing methods is required to carry forward computing advances beyond digital accelerators. In this paper we describe how the energy-efficiency of a large class of problems can be improved by employing a hybrid of the discrete and continuous models of computation instead of the ubiquitous, traditional discrete model of computation. We present preliminary analysis of domains and benchmarks that can be accelerated with the new model. Analysis shows that machine learning, physics and up to one-third of SPEC, RMS and Berkeley suite of applications can be accelerated with the new hybrid model.
    No preview · Article · Jan 2012 · IEEE Computer Architecture Letters
  • Aaron E. Klein · Yannis P. Tsividis
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    ABSTRACT: We present a technique for applying arbitrary in- vertible nonlinear functions to the internal signals of a prototype linear time-invariant digital signal processor, without causing any output disturbances. By using our proposed technique, the external input-output behavior of the DSP remains linear, and identical to that of the prototype, despite the nonlinear behavior of its internal signals. We explore the specific application of our technique to instantaneous companding, in which the introduced nonlinearities compress the dynamic range of the internal signals, so that the latter span most of the available bits in the system, thus improving the signal-to-noise-plus-distortion-ratio at the output, for low to medium input signal levels. We discuss the choice of nonlinear functions for this companding application, and we present an efficient hardware implementation for the standard 15-segment piecewise-linear approximation to the 255- law. We compare the performance and hardware overhead of our technique with that of other companding architectures.
    No preview · Article · Nov 2011 · Circuits and Systems I: Regular Papers, IEEE Transactions on
  • Source
    Christos Vezyrtzis · Aaron E. Klein · Dan Ellis · Yannis P. Tsividis
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    ABSTRACT: We present techniques for processing MPEG-audio encoded signals during the decoding process, using efficient fixed-point arithmetic operations. A large signal-to-quantization-noise-ratio is achieved over a large range of input levels. By taking advantage of MPEGaudio built-in properties, quantization distortion at the outputs of our systems is kept largely inaudible, even though only low-resolution fixed-point operations are used in the processing.
    Preview · Conference Paper · May 2011
  • Mariya Kurchuk · Colin Weltin-Wu · Dominique Morche · Yannis P. Tsividis
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    ABSTRACT: GHz-range applications that operate in a variety of signal situations and/or multiple standards require highly programmable responses that cannot be provided by analog circuits. Conventional digital solutions suffer from aliasing, thus requiring a complicated antialiasing filter and/or extremely high clock speeds with high power dissipation. An alternative is continuous-time (CT) DSP [1], which uses level-crossing sampling [2] but without a clock. It offers activity dependent power dissipation, is alias-free and has lower EMI emissions. This technique has so far been demonstrated in the voice band [3] but cannot be pushed beyond the MHz range because it involves extremely narrow pulse widths that cannot be handled by digital logic. This work bypasses this timing problem, enabling a five-orders-of-magnitude improvement in frequency capa bility compared to [3], thus making CT DSP a candidate for wideband GHz low dynamic-range applications, such as those found in pulse radio, spectrum sens ing, and channel equalization. Presented is a 3b 6-tap CT DSP system with wide programmability that is implemented in ST 65nm technology.
    No preview · Conference Paper · Feb 2011
  • Aaron E. Klein · Yannis Tsividis
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    ABSTRACT: We present a technique whereby internal signals in a DSP can be externally controlled without causing any output disturbances. While the resulting system is in general internally time-varying or internally nonlinear, the external input-output behavior is time-invariant and identical to that of the prototype linear time invariant (LTI) system. Our technique can be used to dynamically scale the input, output, and all internal states of a fixed-point DSP such that they always stay close to full scale, thus spanning most of the available bits and making possible a large signal-to-noise-plus-distortion ratio (SNDR) over a large (external) input range. We show that this application of our technique is an extension of companding (compressing/expanding) to DSPs. A hardware implementation of a companding DSP is presented. At low and medium signal levels, the output SNDR of our companding DSP is significantly larger than that of the corresponding classical DSP using the same number of bits.
    No preview · Article · Oct 2010 · IEEE Transactions on Signal Processing
  • Yannis Tsividis
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    ABSTRACT: Event-driven analog-to-digital conversion and associated digital signal processing techniques are reviewed. Such techniques, still in the research stage, have the potential to significantly reduce the consumption of energy and bandwidth resources in several important applications.
    No preview · Article · Sep 2010 · Circuits and Systems II: Express Briefs, IEEE Transactions on
  • Mariya Kurchuk · Yannis Tsividis
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    ABSTRACT: This paper proposes an energy-efficient asynchronous tunable delay element architecture, appropriate for low-to high-speed digital applications. The delay is made controllable via control currents. The presented delay cell improves upon the efficient thyristor-like-based circuits in prior art by reusing the charge supplied on one edge of the input during the next edge of the input. Over 50% energy reduction is achieved.
    No preview · Conference Paper · Jul 2010
  • Yannis Tsividis
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    ABSTRACT: We present a tutorial review of digital signal processing in continuous time, and associated analog-to-digital conversion. The systems presented do no utilize a clock and are fully event-driven, with power dissipation that adapts to the input signal automatically. An integrated view of several related techniques is offered.
    No preview · Conference Paper · Jul 2010
  • Mariya Kurchuk · Yannis Tsividis
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    ABSTRACT: A variable-resolution (VR) quantizer with input-activity-dependent adjustable resolution is presented. Several potential schemes are discussed; the favored scheme achieves adjustable resolution by level skipping according to the speed of the input. The advantages of a VR analog-to-digital conversion (ADC) are presented with applications in continuous-time (CT) digital signal processing systems. It is shown that a decrease in resolution for fast inputs does not corrupt the in-band spectrum while leading to a reduction in the number of samples produced by a CT ADC. The result is a significant decrease in power dissipation but without in-band performance degradation. Analysis and extensive simulations are provided. Simulations using signals in the voice band show that a power reduction of over 80% is achievable with a VR quantization.
    No preview · Article · Jun 2010 · Circuits and Systems I: Regular Papers, IEEE Transactions on
  • Mariya Kurchuk · Yannis P. Tsividis

    No preview · Article · Jan 2010

Publication Stats

4k Citations
168.38 Total Impact Points

Institutions

  • 1983-2015
    • Columbia University
      • Department of Electrical Engineering
      New York, New York, United States
  • 2005
    • CUNY Graduate Center
      New York City, New York, United States
  • 2001
    • Sony Corporation
      Edo, Tōkyō, Japan
  • 1992-1999
    • National Technical University of Athens
      • • School of Electrical and Computer Engineering
      • • Division of Computer Science
      Athens, Attiki, Greece
  • 1993-1996
    • Budapest University of Technology and Economics
      Budapeŝto, Budapest, Hungary
  • 1982
    • Massachusetts Institute of Technology
      • Department of Electrical Engineering and Computer Science
      Cambridge, Massachusetts, United States