[Show abstract][Hide abstract] ABSTRACT: For the first time, the DRAM device composed of 6F<sup>2</sup> open-bit-line memory cell with 80nm feature size is developed. Adopting 6F<sup>2</sup> scheme instead of customary 8F<sup>2</sup> scheme made it possible to reduce chip size by up to nearly 20%. However, converting the cell scheme to 6F<sup>2</sup> accompanies some difficulties such as decrease of the cell capacitance, and more compact core layout. To overcome this strict obstacles which are originally stemming from the conversion of cell scheme to 6F<sup>2</sup>, TIT structure with AHO (AfO/AlO/AfO) is adopted for higher cell capacitance, and bar-type contact is adopted for adjusting to compact core layout. Moreover, to lower cell V<sub>th</sub> so far as suitable for characteristic of low power operation, the novel concept, S-RCAT (sphere-shaped-recess-channel-array transistor) is introduced. It is the improved scheme of RCAT used in 8F<sup>2</sup> scheme. By adopting S-RCAT, V<sub>th</sub> can be lowered, SW, DIBL are improved. Additionally, data retention time characteristic can be improved.
[Show abstract][Hide abstract] ABSTRACT: For the first time, S-RCAT (sphere-shaped-recess-channel-array transistor) technology has been successfully developed in a 2Gb density DRAM with 70nm feature size. It is a modified structure of the RCAT (recess-channel-array transistor) and shows an excellent scalability of recessed-channel structure to sub-50nm feature size. The S-RCAT demonstrated superior characteristics in DIBL, subthreshold swing (SW), body effect, junction leakage current and data retention time, comparing to the RCAT structure, in this paper, S-RCAT is proved to be the most promising DRAM array transistor suitable for sub-50nm and mobile applications.
[Show abstract][Hide abstract] ABSTRACT: The technology innovation for extending the RCAT structure to the sub-70nm DRAM is presented. The new technology overcomes the problems induced by shrinkage of the RCAT structure and meets the requirements for the next generation DRAMs, such as high speed and low power performance. The technology roadmap down to the 50nm DRAM feature size of the RCAT development is presented.
[Show abstract][Hide abstract] ABSTRACT: Fully reliable lean-free stacked capacitor, with the meshes of the supporter made of Si<sub>3</sub>N<sub>4</sub>, has been successfully developed on 80nm COB DRAM application. This novel process terminates persistent problems caused by mechanical instability of storage node with high aspect ratio. With Mechanically Enhanced Storage node for virtually unlimited Height (MESH), the cell capacitance over 30fF/cell has been obtained by using conventional MIS dielectric with an equivalent 2.3nm oxide thickness. This inherently lean-free capacitor makes it possible extending the existing MIS dielectric technology to sub-70nm OCS (one cylindrical storage node) DRAMs.
[Show abstract][Hide abstract] ABSTRACT: For the first time, novel robust capacitor (Leaning exterminated Ring type Insulator - LERI) and new storage node (SN) contact process (Top Spacer Contact - TSC) are successfully developed with 82nm feature size. These novel processes drastically improved electrical characteristics such as cell capacitance, parasitic bit line capacitance and cell contact resistance, compared to a conventional process. The most pronounced effect using the LERI in COB structure is to greatly improve cell capacitance without twin bit failure. In addition, the TSC technology has an ability to remove a critical ArF lithography. By using the LERI and TSC processes in 82nm 512M DDR DRAM, the cell capacitance of 32fF/cell is achieved with Toxeq of 2.3nm and the parasitic bit line capacitance is reduced by 20%, resulted in great improvement of tRCD (1.5ns).
[Show abstract][Hide abstract] ABSTRACT: For the first time, fully working 512 Mb DRAMS have been developed successfully using an 80 nm DRAM technology, which is the smallest feature size in DRAM technology ever reported. With an ArF lithography, recess-channel-array-transistors (RCAT), low-temperature MIS capacitor technologies and a newly developed top spacer storage node contact (TSC), we have realized these 512 Mb DRAMS. Also, we have reduced process steps, including the layer requiring ArF lithography, by using the TSC process.
[Show abstract][Hide abstract] ABSTRACT: Full integration of a 512-Mb dynamic random access memory (DRAM) using both a raised source-drain (S/D) in a cell and a support area with additional Co silicidation in the support area is successfully performed for the first time at an 88-nm technology node. The Co-silicided support transistors in the DRAM circuit can be made by using the silicidation-blocking-layer method which keeps the cell array from silicidation. Raised S/D transistors using Si selective epitaxial growth (SEG) demonstrate good short-channel effect (SCE) immunity and a Co-silicided S/D in the support transistors exhibits an excellent current driving capability and reduced S/D sheet resistance, even for very small dimensions.
[Show abstract][Hide abstract] ABSTRACT: For the first time, 512 Mb DRAMs using a Recess-Channel-Array-Transistor(RCAT) are successfully developed with 88 nm feature size, which is the smallest feature size ever reported in DRAM technology with non-planar array transistor. The RCAT with gate length of 75 nm and recessed channel depth of 150 nm exhibits drastically improved electrical characteristics such as DIBL, BV<sub>DS</sub>, junction leakage and cell contact resistance, comparing to a conventional planar array transistor of the same gate length. The most powerful effect using the RCAT in DRAMs is a great improvement of data retention time. In addition, this technology will easily extend to sub-70 nm node by simply increasing recessed channel depth and keeping the same doping concentration of the substrate.