[Show abstract][Hide abstract] ABSTRACT: a b s t r a c t Strain engineering in MOSFETs using tensile nitride overlayer (TOL) films, compressive nitride overlayer (COL) films, and embedded-SiGe (eSiGe) is studied by extensive device experiments and numerical simu-lations. The scaling behavior was analyzed by gate length reduction down to 40 nm and it was found that drive current strongly depends on the device dimensions. The reduction of drain-current enhancement for short-channel devices can be attributed to two competing factors: shorter gate length devices have increased longitudinal and vertical stress components which should result in improved drain-currents. However, there is a larger degradation from external resistance as the gate length decreases, due to a larger voltage dropped across the external resistance. Adding an eSiGe stressor reduces the external resistance in the p-MOSFET, to the extent that the drive current improvement from COL continues to increase even down the shortest gate length studied. This is due to the reduced resistivity of SiGe itself and the SiGe valence band offset relative to Si, leading to a smaller silicide-active contact resistance. It demonstrates the advantage of combining eSiGe and COL, not only for increased stress, but also for parasitic resistance reduction to enable better COL drive current benefit.
Full-text · Article · Dec 2008 · Materials Science and Engineering B
[Show abstract][Hide abstract] ABSTRACT: An optimized 4-way stress integration on partially-depleted SOI (PD-SOI) CMOS is presented. An embedded-SiGe process and a compressive-stressed liner film are used to induce compressive strain in the PMOS (PMOS "stressors"). A stress memorization process and a tensile-stressed liner film are used to induce tensile strain in the NMOS (NMOS "stressors"). With optimization, the different stress techniques are highly compatible and additive to each other, improving PMOS and NMOS saturation drive current by 53% and 32%, respectively. This improvement results in 40% higher product speed. To demonstrate the extendibility for future transistor nodes the stress improvements were increased further resulting in record PMOS performance of IDSAT=860muA/mum at 200nA IOFF (self-heating corrected) and 1V. The stress techniques are proven in AMD's 90nm manufacturing processes, and have been scaled for use in 65nm manufacturing
[Show abstract][Hide abstract] ABSTRACT: A high performance 65 nm SOI CMOS technology is presented. Dual stress liner (DSL), embedded SiGe, and stress memorization techniques are utilized to enhance transistor speed. Advanced-low-K BEOL for this technology features 10 wiring levels with a novel K=2.75 film in selected levels. This film is a SiCOH-based dielectric optimized for stress to enable integration for enhanced performance. The resulting technology delivers pFET and nFET AC switching on-current of 735 muA/mum and 1259 muA/mum respectively, at an off-current of 200 nA/um (V<sub>dd</sub>=1.0 V), and 6% reduction in interconnect delay. Process yield is demonstrated on a SRAM cell with size of 0.65 mum<sub>2</sub>
[Show abstract][Hide abstract] ABSTRACT: For the first time, tensile and compressively stressed nitride contact liners have been simultaneously incorporated into a high performance CMOS flow. This dual stress liner (DSL) approach results in NFET/PFET effective drive current enhancement of 15%/32% and saturated drive current enhancement of 11%/20%. Significant hole mobility enhancement of 60% is achieved without using SiGe. Inverter ring oscillator delay is reduced by 24% with DSL. Overall yield for the DSL process is comparable to that of a similar technology without DSL. Single and multi-core SOI microprocessors are being manufactured using the DSL process in multiple, high-volume fabrication facilities.
[Show abstract][Hide abstract] ABSTRACT: Partially depleted (PD) SOI technologies are mature for production of high speed, low power microprocessors. The paper highlights several challenges found during the course of development of a PD 90nm SOI technology. The technology features highly advanced transistors using strained Si and a gate length of sub 45nm with a nine layer low k hackend. By optimizing the strained Si process and overall processing we have achieved yield equal than conventional technologies but with higher performance. The technology was developed for the 64bit Opteron™ and Athlon™ 64 microprocessors.