[Show abstract][Hide abstract] ABSTRACT: We present solutions to the key process technology challenges of three-dimensional (3D) integrated circuits (ICs) that enable creation of stacked device layers with the shortest distance between them, the highest interconnection density and extremely aggressive wafer-to-wafer alignment. To achieve this important 3D IC technology milestone, we optimized the layer transfer process to include a glass handle wafer, oxide fusion bonding, wafer bow compensation methods, and a single damascene patterning and metallization method for creation of high-aspect-ratio (6:1 < AR < 11:1) contacts between two stacked device layers
[Show abstract][Hide abstract] ABSTRACT: Novel silicon-on-insulator (SOI) structures are presented on hybrid orientation substrates (SuperHOT), i.e. with nFETs on (100) surface orientation and pFETs on (110) orientation, using silicon lateral overgrowth. Functional SOI MOSFETs and ring oscillators are demonstrated
[Show abstract][Hide abstract] ABSTRACT: IBM's approach to 3D IC fabrication is based on a wafer-level assembly methodology, where each component is built in parallel but on a separate wafer with its optimized processing technology, followed by layer thinning, alignment, bonding, and vertical interconnection of the active circuit layers to create a new high functionality system. The 3D IC wafer-scale integration is still a relatively new technology and many integration as well as the circuit design choices still require optimization. IBM's goal is to identify and implement manufacturing solutions for: 1) thinning and wafer-level transfers of active device layers, 2) high precision alignments for stacking of these device layers, 3) high strength bond integrity between joined circuit layers, 4) reliable interconnection between active IC layers, including via patterning, metallization, and alignment, as well as 5) optimized circuit/device architectures. To accomplish these goals a variety of test structures have been created' to evaluate: inter-device layer alignment precision, noise & electrical cross-talk between stacked active device layers, and thermal effects, i.e. self-heating and spread-heating in the 3D IC geometry.