Publications (2)0 Total impact
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ABSTRACT: Among the most important design parameters in cache memories are storage capacity, associativity, and line size. Conventional caches are tuned to provide fast performance across a variety of representative applications; however, there is no fixed cache configuration that best fits the varying memory requirements of every application. In this paper we study the potential performance benefits of using an adaptive cache that dynamically adjusts its line length to better match the spatial locality of any memory access of a running application. In our L2 cache model, a group of fixed-size cache lines can be concatenated to form longer lines called superlines. We develop an optimistic reference lookahead technique to determine the optimal superline size for every cache miss. The effectiveness of alternative superline length adjustment strategies could then be measured against this theoretical "best case" strategy. Our results show that a cache with adaptive line size can improve the hit rate in up to 3.25%, and produce speedups of up to 14%
Conference Paper: A Multilevel DRAM with Hierarchical Bitlines and Serial Sensing.[Show abstract] [Hide abstract]
ABSTRACT: We propose a multilevel DRAM (MLDRAM) with serial sensing that has lower area overhead than designs that use single-step, flash conversion sensing. The new design exploits hierarchical, multidivided bitlines to offset the reduction in noise margins caused by multilevel signaling and thereby better preserve the signal-to-noise ratio. The multiple sensing operations required to recover multilevel data are performed serially to re-use sense amplifiers and hence minimize the area overhead of the peripheral circuitry at the cost of increased total read time. In a variation of the proposed design, a subset of the addressed row of cells is read in one sensing step while the remaining cells are recovered later in further sensing steps.