[Show abstract][Hide abstract] ABSTRACT: A full-rate 10 Gb/s transceiver core employing a tri-state binary PD with 100ps gated digital output is implemented in a 90nm CMOS process. Direct drive from the VCO is utilized to eliminate the 10GHz clock buffer current. The RX exhibits a recovered-clock jitter of 906fs<sub>rms</sub> and an input sensitivity of 5.9mV<sub>pp</sub>. The TX generates a jitter of 5mUI<sub>rms</sub>. The chip consumes 250mW.
[Show abstract][Hide abstract] ABSTRACT: A DSSS UWB transceiver using the 3.1 to 5 GHz band is implemented in 0.18 μm CMOS and includes a programmable pulse shaping circuit in the transmitter, an LNA with a NF of 4 dB and a 6<sup>th</sup>-order active LPF with a bandwidth of 500 MHz in the receiver. Die area of the transceiver is around 9 mm<sup>2</sup>. and the transceiver consumes 105 mW in the transmit mode and 280 mW in the receive mode from a 1.8 V supply.