[Show abstract][Hide abstract] ABSTRACT: A phase-locked loop front-end including a LC voltage controlled oscillator and an I-Q injection locked frequency divider is presented. The operation ranges of the VCO and ILFD are aligned by co-designing the tank, specifically the tunable varactors. The total locking range of the front-end is 37.6 to 42.2 GHz which corresponds to a down-conversion range from 56.4 to 63.3 GHz at 60 GHz, thus covering the complete ISM band. The front-end phase noise for a VCO frequency of 39.8 GHz is -102 dBc/Hz at 1 MHz offset. The DC power consumption of the VCO and Q-ILFD is 6mW and 9mW from a 1.2 V supply, respectively. Implemented in a bulk CMOS 65nm technology, the circuit occupies an area of 0.7 × 0.5 mm2.
Preview · Article · Dec 2010 · Waves in Random and Complex Media
[Show abstract][Hide abstract] ABSTRACT: A dual-mode mm-wave injection locked frequency divider operating at 39.5 and 59.5 GHz is presented. Achieving a locking range of 18% and 20% in divide-by-2 and 3 modes, it consumes 4 mW from a 0.8 V supply. Implemented in a bulk CMOS 65 nm technology, it occupies a core area of 0.03 mm<sup>2</sup>. The dual-mode operation is enabled by differential direct injection and Miller capacitance de-tuning. Two new figure-of-merits for proper comparison of ILFDs are also presented.
[Show abstract][Hide abstract] ABSTRACT: This paper presents a wideband 40 GHz divide-by-2 quadrature injection locked frequency divider (Q-ILFD) as an enabling component for sliding-IF 60 GHz transceivers. The design incorporates direct injection topology and input power matching using interconnect inductances to enhance injection efficiency. This results in an excellent input sensitivity and a wide locking range. Fabricated in a 65 nm bulk CMOS technology, the divider operates from 30.3 to 44 GHz (37% locking range) while consuming 9 mW from a 1.2 V supply. The measured phase noise is -131 dBc/Hz at 1-MHz offset whereas the phase error between I-Q outputs is less than 1.44Â°.
[Show abstract][Hide abstract] ABSTRACT: This paper discusses the importance of chip-level EM-simulations required at millimetre wave frequencies for achieving correct results. The negative impact of interconnects on passive structures and the inability of the conventional RC-extraction to cater their effects necessitate alternative solutions. Furthermore during IC-measurements the number of probing points is limited; therefore chip-level simulations can provide insight into circuit behaviour at any point in the circuit. In this work, a non-oscillating 60 GHz transformer coupled I-Q VCO is used as a test-case and it is proved that carrying out EM-simulations for the complete circuit can provide valuable information during the design phase. Sonnet® and Advanced Design Systems® are utilized for EM-simulations and postprocessing functions, respectively.
[Show abstract][Hide abstract] ABSTRACT: The promising high data rate wireless applications at millimeter wave frequencies in general and 60 GHz in particular have gained much attention in recent years. However, challenges related to circuit, layout and measurements during mm-wave CMOS IC design have to be overcome before they can become viable for mass market. 60-GHz CMOS Phase-Locked Loops focusing on phase-locked loops for 60 GHz wireless transceivers elaborates these challenges and proposes solutions for them. The system level design to circuit level implementation of the complete PLL, along with separate implementations of individual components such as voltage controlled oscillators, injection locked frequency dividers and their combinations, are included. Furthermore, to satisfy a number of transceiver topologies simultaneously, flexibility is introduced in the PLL architecture by using new dual-mode ILFDs and switchable VCOs, while reusing the low frequency components at the same time.
[Show abstract][Hide abstract] ABSTRACT: A 60 GHz I-Q VCO covering the frequency range from 57.5 to 63.1 GHz is presented. It exhibits a phase noise of - 95.3 dBc/Hz at 1 MHz offset from a 57.5 GHz carrier. Fabricated in a 65 nm bulk CMOS process, the two VCO-cores consume 30 mA in total from a 1.2 V supply.
[Show abstract][Hide abstract] ABSTRACT: A 54.6 GHz divide-by-3 injection locked frequency divider with low power consumption is presented. A resistive feedback is implemented to achieve a stable dc input and higher injection efficiency. Compared with the conventional design, it exhibits a better supply voltage rejection and wider locking range while a small silicon area is maintained. Fabricated in a TSMC 65 nm bulk CMOS process, this divider operates from 48.8 to 54.6 GHz and consumes 3 mW from a 0.9 V supply.
No preview · Article · Oct 2009 · IEEE Microwave and Wireless Components Letters
[Show abstract][Hide abstract] ABSTRACT: This paper presents two monolithic transformer structures exhibiting high self resonance frequencies(fSR). Effect of positive and negative coupling factor on self resonance frequency is investigated. The transformer turn ratio and structure is selected to improve design and ease layout of a high frequency LNA and VCO. Measurement results of a transformer show good agreement with simulated values and demonstrate a coupling factor of 0.7 at 20 GHz.
[Show abstract][Hide abstract] ABSTRACT: This paper presents a low power, low phase noise mm-wave voltage controlled oscillator. The VCO can be tuned from 41 to 44.5 GHz (8% tuning range) and utilizes a differential tuning mechanism based on varactors and fixed MIM capacitors. Fabricated in a bulk CMOS 65 nm technology, it consumes 3.6 mW and exhibits a phase noise of -106 dBc/Hz at 1 MHz offset from a 41.2 GHz carrier. The resulting FOM is -192.7 dBc/Hz, which is the best reported value for VCOs operating above 40 GHz.
[Show abstract][Hide abstract] ABSTRACT: This paper presents a broadband, highly linear amplifier suitable for multi-standard mm-wave applications such as car radar, LMDS and satellite return channel. It can also be utilized as an efficient wideband output buffer, for measurements of mm-wave circuit components. It exhibits a 3-dB bandwidth of 40 GHz with a pass-band gain of 6 dB. The presented amplifier is highly linear with an IP3 of +18 dBm. It has been implemented in a bulk 90 nm CMOS LP (low power) technology and consumes 3.3 mW from a 1.2 V supply.
[Show abstract][Hide abstract] ABSTRACT: In this work, new receiver concepts and key building blocks, at circuit level, for future millimeter-wave wireless communications standards are introduced. Starting from passive and active devices, trade-offs between technology, performance and circuit choices of millimeter-wave RF front-end circuits are discussed. In particular, power consumption, noise and linearity trade-offs in low-noise amplifiers, mixers, frequency dividers and oscillators are considered. The concepts derived are applied to a large class of wireless communications standards that are broadband in nature at RF and/or require a broadband IF.
[Show abstract][Hide abstract] ABSTRACT: This paper presents a broadband, static, 2:1 frequency divider in a bulk 90 nm CMOS LP (low-power) technology with maximum operating frequency of 35.5 GHz. The divider exhibits an enhanced input sensitivity, below 0 dBm, over a broad input range of 31 GHz and consumes 24 mA from a 1.2 V supply. The phase noise of the divider is -124.6 dBc/Hz at 1 MHz offset from the carrier.
[Show abstract][Hide abstract] ABSTRACT: A mm-wave VCO tunable from 41 to 44.5 GHz (8% tuning range) is presented. It utilizes a differential tuning mechanism based on varactors and fixed MIM capacitors. Fabricated in a bulk CMOS 65nm technology, it consumes 3.6 mW and exhibits a phase noise of -106 dBc/Hz at 1 MHz offset from a 41.2 GHz carrier. The resulting FOM is -192.7 dBc/Hz, which is the best reported value for VCOs operating above 40 GHz. Twenty-nine samples are measured to analyze die-to-die variations of the VCO and results are presented.