Eugene A. Imhoff

United States Naval Research Laboratory, Washington, Washington, D.C., United States

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Publications (25)37.06 Total impact

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    ABSTRACT: The conversion of basal plane dislocations (BPDs) to electrically benign threading edge dislocations in 4 degrees off-axis 4HSiC epilayers has been investigated using ultraviolet photoluminescence imaging. The conversion spontaneously occurred throughout the epitaxial layer for all substrates studied using similar epitaxial growth conditions. BPD conversion in highly doped epilayers was suppressed compared with lower n-type doped layers, suggesting that nitrogen concentration influences the conversion mechanism. However, it is technologically important for the conversion to occur in a heavily doped buffer layer. The densities of BPDs in low-doped (similar to 10 (14)cm3) films having a thickness of 20 mu m were significantly reduced when a similar to 20 mu m thick highly doped N+ buffer layer was grown between the low-doped layer and the substrate. Without the buffer layer, an average of similar to 50 BPDs cm2 was observed and with the buffer layer, an average of 1.5 BPDs cm2 was detected; the best result was 0.2 BPD cm(-2). A PiN structure consisting of a 25 mu m thick N+ buffer layer to convert the majority of BPDs prior to the device structure was used to test the mitigation process, and the diodes demonstrated no forward voltage change after 225 h of continuous biasing at 100 A cm(-2).
    No preview · Article · Nov 2014 · Crystal Growth & Design
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    ABSTRACT: High temperature annealing of carbon capped SiC epilayers was performed using multi-cycle rapid thermal annealing technique to eliminate basal plane dislocations (BPD) and preserve the surface morphology. Annealing was performed in temperature range of 1750 °C - 1875 °C at N2 overpressure of 0.55MPa and 0.7MPa. BPDs in the epilayers were found to be eliminated for annealing at 1875 °C for 5 mins with 20 multiple heating cycles under 0.55MPa N2 overpressure. Under high temperature annealing, the BPDs convert to threading edge dislocations, which glides in the epilayers as the BPD retracts towards the substrate.
    No preview · Article · Aug 2014 · ECS Transactions
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    K.D. Hobart · E.A. Imhoff · B. Ray
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    ABSTRACT: Medium voltage SiC Junction Barrier Schottky (JBS) diodes are considered as a replacement for conventional Si freewheeling PiN diodes in phase-leg applications. While lower voltage SiC Schottky diodes are commercially available, medium voltage SiC JBS diodes are also attractive due to their relative simplicity and thus potential for low cost. In this work, the performance of 4.5 kV SiC JBS diodes paired with Si IGBTs is reviewed and compared to legacy components. Hybrid Si/SiC module design and performance are reviewed and potential reliability issues are examined.
    Preview · Article · Aug 2014 · ECS Transactions
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    ABSTRACT: Basal Plane Dislocations (BPD) were reduced in 4H-SiC epilayers by high temperature annealing in the range of 1600 °C to 1950 °C using two annealing techniques. Samples annealed at > 1750 °C showed almost complete elimination of BPDs propagating from the substrate. However, surface morphology was degraded for MW annealed samples above 1800 °C, with new BPDs being generated from the surface. A new capping technique was developed along with application of high N2 overpressure to preserve the surface morphology and avoid formation of new BPDs.
    No preview · Article · Feb 2014 · Materials Science Forum
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    ABSTRACT: Basal plane dislocations (BPD) were mostly eliminated in 4H-SiC epitaxy using post growth high temperature annealing in the range of 1600 degrees C - 1950 degrees C for 30s - 2 mins. The samples annealed at temperatures >1700 degrees C showed the best BPD reduction. However, surface morphology was degraded for samples annealed >1850 degrees C, and new BPDs were generated. A better capping technique was developed to improve the surface morphology and avoid generation of new BPDs, while significantly reducing the existing BPDs in the SiC epitaxial layers.
    No preview · Conference Paper · Oct 2013
  • K. D. Hobart · E. A. Imhoff · T. H. Duong · A. R. Hefner
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    ABSTRACT: The optimization of medium voltage hybrid Si IGBT/SiC junction barrier Schottky diode modules is explored. The primary variant in the study is the active device area of the SiC JBS diodes for a fixed Si IGBT area. The optimization is performed through electro-thermal circuit simulations using validated physics-based device models. Parameters tracked include device switching losses, conduction losses and junction temperature. Finally, reliability issues were considered. SiC JBS diodes were subject to surge conditions and diode surge current was evaluated during module optimization.
    No preview · Article · Mar 2013 · ECS Transactions
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    ABSTRACT: There has been significant research in the study of in-plane charge-carrier transport in graphene in order to understand and exploit its unique electrical properties; however, the vertical graphene-semiconductor system also presents opportunities for unique devices. In this letter, we investigate the epitaxial graphene/p-type 4H-SiC system to better understand this vertical heterojunction. The I-V behavior does not demonstrate thermionic emission properties that are indicative of a Schottky barrier but rather demonstrates characteristics of a semiconductor heterojunction. This is confirmed by the fitting of the temperature-dependent I-V curves to classical heterojunction equations and the observation of band-edge electroluminescence in SiC.
    No preview · Article · Nov 2012 · IEEE Electron Device Letters
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    ABSTRACT: Integration of patterned ballast resistance into the anode of SiC PiNs is a solution to the dilemma of negative dVf /dT for such diodes. In fabricated 4H-SiC PiN diodes, we demonstrate a cross-over from negative to positive temperature coefficient for current densities as low as 80 A/cm2. Adjusting the percentage of the patterned anode area, the positive or neutral dVf /dT can be achieved over a wide current-density range without substantial penalty in the forward voltage drop. This characteristic is crucial for high-power SiC packages with ganged-parallel rectifier arrays.
    No preview · Article · May 2012 · Materials Science Forum
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    ABSTRACT: We demonstrate the first successful growth of large-area (200 × 200 μm(2)) bilayer, Bernal stacked, epitaxial graphene (EG) on atomically flat, 4H-SiC (0001) step-free mesas (SFMs) . The use of SFMs for the growth of graphene resulted in the complete elimination of surface step-bunching typically found after EG growth on conventional nominally on-axis SiC (0001) substrates. As a result heights of EG surface features are reduced by at least a factor of 50 from the heights found on conventional substrates. Evaluation of the EG across the SFM using the Raman 2D mode indicates Bernal stacking with low and uniform compressive lattice strain of only 0.05%. The uniformity of this strain is significantly improved, which is about 13-fold decrease of strain found for EG grown on conventional nominally on-axis substrates. The magnitude of the strain approaches values for stress-free exfoliated graphene flakes. Hall transport measurements on large area bilayer samples taken as a function of temperature from 4.3 to 300 K revealed an n-type carrier mobility that increased from 1170 to 1730 cm(2) V(-1) s(-1), and a corresponding sheet carrier density that decreased from 5.0 × 10(12) cm(-2) to 3.26 × 10(12) cm(-2). The transport is believed to occur predominantly through the top EG layer with the bottom layer screening the top layer from the substrate. These results demonstrate that EG synthesized on large area, perfectly flat on-axis mesa surfaces can be used to produce Bernal-stacked bilayer EG having excellent uniformity and reduced strain and provides the perfect opportunity for significant advancement of epitaxial graphene electronics technology.
    Full-text · Article · Mar 2012 · Nano Letters
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    ABSTRACT: Stacking fault (SF) expansion from basal plane dislocations (BPDs) confined in highly doped 4H-SiC buffer layers is observed under high-power ultraviolet illumination (>1000 W/cm2). Once the SFs reach the active drift layers, grown above the buffer layers, they are seen to rapidly expand up to the sample surface where they can cause device degradation. BPD faulting in the buffer appears to have a carrier injection threshold. Carrier density simulations under various injection conditions and carrier lifetimes are used to establish the conditions of BPD faulting within the buffer layer that could prevent SF expansion into the drift layer.
    Full-text · Article · Jan 2012 · Applied Physics Letters
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    ABSTRACT: As a wide-bandgap semiconductor, gallium nitride (GaN) is an attractive material for next-generation power devices. To date, the capabilities of GaN-based high electron mobility transistors (HEMTs) have been limited by self-heating effects (drain current decreases due to phonon scattering-induced carrier velocity reductions at high drain fields). Despite awareness of this, attempts to mitigate thermal impairment have been limited due to the difficulties involved with placing high thermal conductivity materials close to heat sources in the device. Heat spreading schemes have involved growth of AIGaN/GaN on single crystal or CVD diamond, or capping of fullyprocessed HEMTs using nanocrystalline diamond (NCD). All approaches have suffered from reduced HEMT performance or limited substrate size. Recently, a "gate after diamond" approach has been successfully demonstrated to improve the thermal budget of the process by depositing NCD before the thermally sensitive Schottky gate and also to enable large-area diamond implementation.
    No preview · Conference Paper · Jan 2012
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    ABSTRACT: A novel taper-doping anode termination method is introduced for high-voltage silicon carbide devices. The method employs a subresolution two-tone termination mask to achieve a gray-scale exposure and a smoothly tapered photoresist profile. Using the tapered profile as an implantation mask, self-aligned 6-kV SiC PiN diodes are demonstrated with 90% of the parallel-plate breakdown voltage. The avalanche breakdown for the design is controlled and reversible. This one-step technique allows wide design control over the width and shape of the termination profile and has wide device and material applicability.
    No preview · Article · Nov 2011 · IEEE Transactions on Electron Devices
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    ABSTRACT: A new 60 A, 4.5 kV SiC JBS diode is presented, and its performance is compared to a Si PiN diode used as the antiparallel diode for 4.5 kV Si IGBTs. The I-V, C-V, reverse recovery, and reverse leakage characteristics of both diode types are measured. The devices are also characterized as the anti-parallel diode for a 4.5 kV Si IGBT using a recently developed high-voltage, double-pulse switching test system. The results indicate that SiC JBS diodes reduce IGBT turn-on switching loses by about a factor of three in practical applications. Furthermore, the peak IGBT current at turn-on is typically reduced by a factor of six, resulting in substantially lower IGBT stress. Circuit simulator models for the 4.5 kV SiC JBS and Si PiN diodes are also developed and compared with measurements.
    No preview · Article · Mar 2011
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    ABSTRACT: Shockley Stacking fault (SSF) expansion from basal plane dislocations (BPDs) occurs during forward bias operation in 4H-Silicon Carbide (SiC) and causes forward voltage drift in minority carrier SiC devices [1, 2]. Reverse bias breakdown voltage degradation with SSF expansion has also been reported [3]. The SSFs expansion occurs via the electron-hole recombination enhanced dislocation glide (REDG) process [4]. In order to mitigate the influence of these SSFs in the active drift layer, a high doped buffer layer was grown to convert most of the BPDs to threading edge dislocations (TED) within it. This confines the BPD to the buffer and only the relatively benign TED passes through the drift layer. Previously it was thought that SSF expansion would not occur in these high doped epilayers and propagate into the drift layer. However, this assumption that BPDs within the buffer do not affect the drift layer during carrier injection has not been previously studied. In this work using electron-hole creation by UV excitation, we image the motion and faulting of BPDs buried in the buffer layer and show that SFs originating in that layer expand into the device drift region.
    No preview · Conference Paper · Jan 2011
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    ABSTRACT: High voltage GaN Schottky diodes require a thick blocking layer with an exceptionally low carrier concentration. To this aim, a metal organic chemical vapor deposition process was developed to create a (14 μm) thick stress-free homoepitaxial GaN film. Low temperature photoluminescence measurements are consistent with low donor background and low concentration of deep compensating centers. Capacitance–voltage measurements performed at 30 °C verified a low level of about 2×1015 cm−3 of n-type free carriers (unintentional doping), which enabled a breakdown voltage of about 500 V. A secondary ion mass spectrometry depth profile confirms the low concentration of background impurities and X-ray diffraction extracted a low dislocation density in the film. These results indicate that thick GaN films can be deposited with free carrier concentrations sufficiently low to enable high voltage rectifiers for power switching applications.
    Preview · Article · Sep 2010 · Journal of Crystal Growth
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    ABSTRACT: Carrier traps in 4H-SiC metal–oxide–semiconductor (MOS) capacitor and transistor devices were studied using the thermally stimulated current (TSC) method. TSC spectra from p-type MOS capacitors and n-channel MOS field-effect transistors (MOSFETs) indicated the presence of oxide traps with peak emission around 55K. An additional peak near 80K was observed due to acceptor activation and hole traps near the interface. The physical location of the traps in the devices was deduced using a localized electric field approach. The density of hole traps contributing to the 80-K peak was separated from the acceptor trap density using a gamma-ray irradiation method. As a result, hole trap density of N t,hole=2.08×1015cm−3 at 2MV/cm gate field and N t,hole=2.5×1016cm−3 at 4.5MV/cm gate field was extracted from the 80-K TSC spectra. Measurements of the source-body n +–p junction suggested the presence of implantation damage in the space-charge region, as well as defect states near the n + SiC substrate. KeywordsThermally stimulated current-hole traps-4H-SiC MOSCAP-4H-SiC MOSFET-threshold voltage-implantation damage-acceptor activation
    Full-text · Article · May 2010 · Journal of Electronic Materials
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    ABSTRACT: Field-effect transistors were fabricated on GaN and Al(0.2)Ga(0.8)N epitaxial layers grown by metal organic chemical vapor deposition (MOCVD) on sapphire substrates. The threshold voltage V(TH) was higher when AlGaN was used as an active layer. VTH also increased with temperature due to the increased positive polarization charge at the GaN/AlN buffer/sapphire interfaces. Drain current increased at high temperatures even with more positive threshold voltage, which makes GaN-based VET devices attractive for high temperature operation.
    No preview · Article · Apr 2010 · Materials Science Forum
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    ABSTRACT: A polariton-based light emitter is a extraordinary concept as an alternative to a light-emitting diode (LED) or laser diode. The physics of a polariton laser is fundamentally different from the spontaneous emission process of an LED or the inversion and stimulated emission process of a laser diode. The rapid decay and emission from this polariton–exciton state bypasses the normal irreversible spontaneous emission and associated non-radiative decay mechanisms. An AlGaN/AlN nucleation bilayer was employed on r-plane sapphire to deposit non-polar GaN quantum wells embedded in an AlGaN-based cavity surrounded by top and bottom distributed Bragg reflectors (DBRs). The reflectance data show that the exciton and photon states can be tuned (by changing the angle of the sample) to the same energy. The characteristic strong coupling was observed in the reflectance data where the states of the exciton and photon do not overlap; rather they split into an upper polariton state and a lower polariton state. The photoluminescence (PL) showed a strong emission at a low stimulation level at a similar energy and angle.
    No preview · Article · Dec 2009 · Solid State Communications
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    ABSTRACT: The increase in the forward voltage drop observed in 4H -SiC bipolar devices due to recombination-induced stacking fault (SF) creation and expansion has been widely discussed in the literature. It was long believed that the deleterious effect of these defects was limited to bipolar devices. Recent reports point to similar degradation in 4H -SiC DMOSFETs, a primarily unipolar device, which was thought to be SF-related. Here we report similar degradation of both unipolar and bipolar operation of merged- PiN -Schottky diodes, a hybrid device capable of both unipolar and bipolar operation. Furthermore, we report on the observation of the temperature-mediation of this degradation and the observation of the current-induced recovery phenomenon. These observations leave little doubt that this degradation is SF-induced and that if SFs are present, that they will adversely affect both bipolar and unipolar characteristics.
    No preview · Article · Sep 2009 · Journal of Applied Physics
  • Eugene A. Imhoff · Fritz J. Kub · Karl D. Hobart
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    ABSTRACT: In silicon carbide devices used above around 2.4 kV, effective anode edge termination usually requires a high-resolution floating guard ring implant or multiple lithography/implant cycles to effect a multi-zone junction termination extension. In general the goal is to produce a smoothly tapered field profile to prevent high-voltage field-crowding that causes premature breakdown at the edge of the high voltage electrode. Using a much simpler grayscale photolithographic technique and a single termination implant, we directly produce the desired tapered doping profile. The effectiveness of this termination is shown by the near-ideal (6.1 kV) breakdown measured in PiN diodes made with a 38 μm intrinsic layer. The simple method is applicable to the fabrication of many high-voltage devices.
    No preview · Article · Jan 2009 · Materials Science Forum