David H. Seo

Samsung Advanced Institute of Technology, Usan-ri, Gyeonggi-do, South Korea

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Publications (46)260.28 Total impact

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    ABSTRACT: We have investigated single- and bi-layer graphene as source-drain electrodes for n-type MoS2 transistors. Ti-MoS2-graphene heterojunction transistors using both single-layer MoS2 (1M) and 4-layer MoS2 (4M) were fabricated in order to compare graphene electrodes with commonly used Ti electrodes. MoS2-graphene Schottky barrier provided electron injection efficiency up to 130 times higher in the subthreshold regime when compared with MoS2-Ti, which resulted in VDS polarity dependence of device parameters such as threshold voltage (VTH) and subthreshold swing (SS). Comparing single-layer graphene (SG) with bi-layer graphene (BG) in 4M devices, SG electrodes exhibited enhanced device performance with higher on/off ratio and increased field-effect mobility (μFE) due to more sensitive Fermi level shift by gate voltage. Meanwhile, in the strongly accumulated regime, we observed opposing behavior depending on MoS2 thickness for both SG and BG contacts. Differential conductance (σd) of 1M increases with VDS irrespective of VDS polarity, while σd of 4M ceases monotonic growth at positive VDS values transitioning to ohmic-like contact formation. Nevertheless, the low absolute value of σd saturation of the 4M-graphene junction demonstrates that graphene electrode could be unfavorable for high current carrying transistors.
    No preview · Article · Dec 2015 · Applied Physics Letters
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    ABSTRACT: Poly (methyl methacrylate) (PMMA) is commonly used during the transfer process of chemical vapor deposited (CVD) graphene. Since PMMA on graphene surfaces is removed by breaking polymerization backbone bonds (de-polymerization), using shorter polymer chains can be a self-solving method for PMMA residue removal. We report on graphene properties transferred with different average molecular weight poly (methyl methacrylate) (PMMA). We obtained enhanced field effect mobility and reduced hole doping without post-annealing for lower average molecular weight PMMA. Also, the graphene surfaces transferred by lower average molecular weight PMMA was free of polymer debris with clean morphology, which was confirmed by carbon 1s X-ray photoemission spectroscopy. This graphene transfer process can be used to avoid additional thermal budget which can cause degradation of device performance.
    No preview · Article · Nov 2015
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    ABSTRACT: Resistive random access memory (ReRAM) devices have been extensively investigated resulting in significant enhancement of switching properties. However fluctuations in switching parameters are still critical weak points which cause serious failures during 'reading' and 'writing' operations of ReRAM devices. It is believed that such fluctuations may be originated by random creation and rupture of conducting filaments inside ReRAM oxides. Here, we introduce defective monolayer graphene between an oxide film and an electrode to induce confined current path distribution inside the oxide film, and thus control the creation and rupture of conducting filaments. The ReRAM device with an atomically thin interlayer of defective monolayer graphene reveals much reduced fluctuations in switching parameters compared to a conventional one. Our results demonstrate that defective monolayer graphene paves the way to reliable ReRAM devices operating under confined current path distribution.
    Preview · Article · Jul 2015 · Scientific Reports
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    ABSTRACT: Transistor size is constantly being reduced to improve performance as well as power consumption. For the channel length to be reduced, the corresponding gate dielectric thickness should also be reduced. Unfortunately, graphene devices are more complicated due to an extra capacitance called quantum capacitance (C Q) which limits the effective gate dielectric reduction. In this work, we analyzed the effect of C Q on device-scaling issues by extracting it from scaling of the channel length of devices. In contrast to previous reports for metal-insulator-metal structures, a practical device structure was used in conjunction with direct radio-frequency field-effect transistor measurements to describe the graphene channels. In order to precisely extract device parameters, we reassessed the equivalent circuit, and concluded that the on-state model should in fact be used. By careful consideration of the underlap region, our device modeling was shown to be in good agreement with the experimental data. C Q contributions to equivalent oxide thickness were analyzed in detail for varying impurity concentrations in graphene. Finally, we were able to demonstrate that despite contributions from C Q, grapheme’s high mobility and low-voltage operation allows for graphene channels suitable for next generation transistors.
    Preview · Article · Apr 2015 · Nano Research
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    ABSTRACT: Power amplifier circuits are implemented with graphene field-effect transistors (FETs), capacitors and inductors, and their gain is improved step-by-step by adjusting the passive components. The transistors are fabricated on a 150-mm wafer using conventional complementary-metal-oxide semiconductor processing along with graphene transferring processes. The completed circuit is implemented on a printed circuit board, which allows for adjustment of the external capacitance and inductance to study the performance of graphene RF FETs. A maximum signal gain of 1.3 dB is achieved at 380 MHz. The device parameters of the transistors are then extracted and the gain is analyzed, and the results show that lowering the source drain conductance and gate resistance is the key in realizing high performance circuits.
    No preview · Article · Aug 2014 · Current Applied Physics
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    In Kyeong Yoo · Myoung-Jae Lee · David H. Seo · Sung-Jin Kim
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    ABSTRACT: Many attempts have been tried to improve switching characteristics of resistive switching materials such as NiOx because it gives scattered switching current and voltage values [J. F. Gibbons and W. E. Beadle, Solid-State Electron. 7, 785–790 (1964); S. Seo et al., Appl. Phys. Lett. 85, 5655–5657 (2004); H. D. Lee et al., Phys. Rev. B 81, 193202 (2010); S. I. Kim et al., Appl. Phys. Lett. 104, 023513 (2014); M.-J. Lee et al., Nano Lett. 9, 1476–1481 (2009)]. The nature of scattering should be understood based on switching mechanism and the source of scattering in order to improve switching properties. Here, the long tail in scatter data—the data points which are observed only one or two times during switching—was investigated. Techniques such as multiple input pulses are proposed in order to avoid switching missing and size scaling of switching devices are suggested in order to improve data scattering. In addition, discovery of double switching curves in unipolar switching is presented.
    Full-text · Article · Jun 2014 · Applied Physics Letters
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    ABSTRACT: We report on the fabrication of completely uniform monolayer graphene on a metal thin film over a 150 mm Si substrate at a low temperature of 600 degrees C by inductively coupled plasma-enhanced chemical vapor deposition (ICPCVD). Through novel use of bimetallic catalyst such as CuNi and AuNi alloys we were able to control catalytic reaction at the metal surface and grow complete monolayer graphene with a Ni content less than 20 at.%. We also found that the 2D/G intensity ratio in the Raman spectra was almost invariant with growth time and the C 1s peak in the XPS spectra was observed only at the metal surface. This implies that monolayer graphene was possibly grown on these Ni-doped copper and gold catalysts by a self-limiting surface reaction under our CVD condition. From DFT calculations, it was shown that the catalytic activity of normally inactive Cu and Au could be enhanced through the addition of Ni atoms at surface sites, providing graphene growth at lower temperatures than pure Cu or Au. The carrier mobility of graphene films grown on these CuNi and AuNi alloy catalyst was measured to be over 9000 cm(2) V-1 s(-1) at room temperature, which is comparable to that of CVD graphene film grown on Cu foil. Therefore, we suggest an efficient way in growing a complete monolayer graphene on thin films at low temperatures, which could be a key issue in the application of graphene devices.
    No preview · Article · Nov 2013 · Carbon
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    ABSTRACT: Stackable select devices such as the oxide p-n junction diode and the Schottky diode (one-way switch) have been proposed for non-volatile unipolar resistive switching devices; however, bidirectional select devices (or two-way switch) need to be developed for bipolar resistive switching devices. Here we report on a fully stackable switching device that solves several problems including current density, temperature stability, cycling endurance and cycle distribution. We demonstrate that the threshold switching device based on As-Ge-Te-Si material significantly improves cycling endurance performance by reactive nitrogen deposition and nitrogen plasma hardening. Formation of the thin Si3N4 glass layer by the plasma treatment retards tellurium diffusion during cycling. Scalability of threshold switching devices is measured down to 30 nm scale with extremely fast switching speed of ~2 ns.
    Full-text · Article · Oct 2013 · Nature Communications
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    Full-text · Dataset · Sep 2013
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    ABSTRACT: The rectifying Schottky characteristics of the metal-semiconductor junction with high contact resistance have been a serious issue in modern electronic devices. Herein, we demonstrated the conversion of the Schottky nature of the Ni-Si junction, one of the most commonly used metal-semiconductor junctions, into an Ohmic contact with low contact resistance by inserting a single layer of graphene. The contact resistance achieved from the junction incorporating graphene was about 10(-8 ~ -9) Ω cm(2) at a Si doping concentration of 10(17) cm(-3).
    No preview · Article · Aug 2013 · Nano Letters
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    ABSTRACT: Until now, the studies about low-frequency noises in electronic devices have mostly relied on the scaling behaviour analysis of current noise measured from multiple devices with different resistance values. However, the fabrication of such multiple devices for noise analysis is a labor-intensive and time-consuming work. Herein, we developed the scanning noise microscopy (SNM) method for nanoscale noise analysis of electronic devices, which allowed us to measure the scaling behaviour of electrical current noises in a graphene-strip-based device. In this method, a conductive atomic force microscopy probe made a direct contact on the graphene strip channel in the device to measure the noise spectra through it. The SNM method enabled the investigation of the noise scaling behaviour using only a single device. In addition, the nanoscale noise map was obtained, which allowed us to study the effect of structural defects on the noise characteristics of the graphene strip channel. Our method should be a powerful strategy for nanoscale noise analysis and play a significant role in basic research on nanoscale devices.
    No preview · Article · Mar 2013
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    ABSTRACT: A graphene charge-trap memory is devised using a single-layer graphene channel with an Al2O3/AlOx/Al2O3 oxide stack, where the ion-bombarded AlOx layer is intentionally added to create an abundance of charge-trap sites. The low dielectric constant of AlOx compared to Al2O3 reduces the potential drop in the control oxide Al2O3 and suppresses the electron back-injection from the gate to the charge-storage layer, allowing the memory window of the device to be further extended. This shows that the usage of a lower dielectric constant in the charge-storage layer compared to that of the control oxide layer improves the memory performance for graphene charge-trap memories.
    No preview · Article · Dec 2012 · Applied Physics Letters
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    ABSTRACT: Understanding the breakdown current density is not enough for establishing the reliability performance of graphene interconnects. It is more important to know how graphene wires degrade with time under constant current stress and how that compares with conventional interconnects. This letter investigates the lifetime of graphene interconnect under constant high current stress. Under a stress current density of 20 MA/cm2 at 250°C exposed to air, the mean time to fail of a 3-μm-wide 100-μm-long graphene interconnect is approximately 6 h, slightly worse than the extrapolated electromigration lifetime of a copper interconnect capped with CoWP at the same stress current density. Raman study shows that the interconnect failure is mainly caused by defect formation due to graphene oxidation. This suggests that optimizing the capping material for graphene interconnect will substantially improve the reliability lifetime of graphene interconnects.
    No preview · Article · Nov 2012 · IEEE Electron Device Letters
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    ABSTRACT: A transparent and flexible graphene charge-trap memory (GCTM) composed of a single-layer graphene channel and a 3-dimensional gate stack was fabricated on a polyethylene naphtalate substrate below eutectic temperatures (∼110 °C). The GCTM exhibits memory functionality of ∼8.6 V memory window and 30% data retention per 10 years, while maintaining ∼80% of transparency in the visible wavelength. Under both tensile and compressive stress, the GCTM shows minimal effect on the program/erase states and the on-state current. This can be utilized for transparent and flexible electronics that require integration of logic, memory, and display on a single substrate with high transparency and endurance under flex.
    No preview · Article · Aug 2012 · ACS Nano
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    ABSTRACT: Graphene-based non-volatile charge-trap memory devices were fabricated and characterized to investigate the implementation effect of both 2-dimensional graphene and the 3-dimensional memory structure. The single-layer-graphene (SLG) channel devices exhibit larger memory windows compared to the multi-layer-graphene (MLG) channel devices. This originates from the gate-coupling strength being larger in SLG devices than in MLG devices. Namely, the electrostatic charge screening effect becomes enhanced upon increasing the number of graphene layers; therefore, the gate tunability is reduced in MLG compared to SLG. The results suggest that SLG is more desirable for memory applications than MLG.
    No preview · Article · Jul 2012 · Journal- Korean Physical Society
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    ABSTRACT: Lifetime of multi-layer graphene interconnects under constant current stress is studied for the first time. Under a stress current density of 20MA/cm2 at 250°C exposed to air, Mean-Time-To-Fail (MTTF) of uncapped CVD graphene wire is about 6 hours. It is shown that lifetime is mainly limited by defect formation due to graphene oxidation.
    No preview · Conference Paper · Jun 2012
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    ABSTRACT: Despite several years of research into graphene electronics, sufficient on/off current ratio I(on)/I(off) in graphene transistors with conventional device structures has been impossible to obtain. We report on a three-terminal active device, a graphene variable-barrier "barristor" (GB), in which the key is an atomically sharp interface between graphene and hydrogenated silicon. Large modulation on the device current (on/off ratio of 10(5)) is achieved by adjusting the gate voltage to control the graphene-silicon Schottky barrier. The absence of Fermi-level pinning at the interface allows the barrier's height to be tuned to 0.2 electron volt by adjusting graphene's work function, which results in large shifts of diode threshold voltages. Fabricating GBs on respective 150-mm wafers and combining complementary p- and n-type GBs, we demonstrate inverter and half-adder logic circuits.
    Full-text · Article · May 2012 · Science
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    ABSTRACT: A Flexible and Transparent charge trap Memory (FTM) based on a single-layer graphene (SLG) channel with a ITO gate electrode was fabricated on a flexible and transparent poly-ethylene naphtalate (PEN) substrate. Triple high-k dielectric stacks Al2O3- AlOx-Al2O3 (AAA) were used as a data storage layer. The FTM shows memory characteristics with a memory window larger than 7V while maintaining ~80% of its transparency in the visible wavelength. The adoption of an AAA gate stack effectively suppressed the electron back injection from the gate electrode. This can be utilized for transparent and flexible electronics that require integration of logic, memory and display on a single flexible substrate with high transparency.
    No preview · Article · May 2012
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    ABSTRACT: Graphene-based non-volatile memory devices composed of a single-layer graphene channel and an Al2O3/HfOx/Al2O3 charge-storage layer exhibit memory functionality. The impact of the gate material’s work-function (Φ) on the memory characteristics is investigated using different types of metals [Ti (ΦTi = 4.3 eV) and Ni (ΦNi = 5.2 eV)]. The ambipolar carrier conduction of graphene results in an enlargement of memory window (ΔVM), which is ∼4.5 V for the Ti-gate device and ∼9.1 V for the Ni-gate device. The increase in ΔVM is attributed to the change in the flat-band condition and the suppression of electron back-injection within the gate stack.
    No preview · Article · Jan 2012 · Applied Physics Letters
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    ABSTRACT: A The non-volatile gEOTMs are fabricated using a single-layer graphene (SLG) channel with an Al2O3 gate oxide layer, in which an ion-bombarded AlOx layer is intentionally formed by oxygen ion bombardment (OIB) to create the charge trap sites. The whole processes are carried out at temperature below 120°C to exploit gEOTM's compatibility to the flexible substrates. The devices shows a large memory window (> 11.0 V), attributing to the effective electron-injection into the trap sites in AlOx. The results suggest that the gEOTM has potential applications for the high-density-memory devices and modules in flexible electronics.
    No preview · Article · Jan 2012

Publication Stats

3k Citations
260.28 Total Impact Points


  • 2004-2014
    • Samsung Advanced Institute of Technology
      Usan-ri, Gyeonggi-do, South Korea
  • 2012
    • SAIT Polytechnic
      Calgary, Alberta, Canada
  • 2009-2010
    • Stanford University
      • • Solid State and Photonics Laboratory
      • • Department of Materials Science and Engineering
      Palo Alto, CA, United States
  • 2005
    • Konkuk University
      • School of Physics
      Sŏul, Seoul, South Korea