Belén Pérez Verdú

Barcelona Microelectronics Institute, Barcino, Catalonia, Spain

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Publications (30)3.34 Total impact

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    ABSTRACT: Avalanche diodes operating in Geiger mode are able to detect single photon events. They can be employed to photon counting and time-of-flight estimation. In order to ensure proper operation of these devices, the avalanche current must be rapidly quenched, and, later on, the initial equilibrium must be restored. In this paper, we present an active quenching/recharge circuit specially designed to be integrated in the form of an array of single-photon avalanche diode (SPAD) detectors. Active quenching and recharge provide benefits like an accurately controllable pulse width and afterpulsing reduction. In addition, this circuit yields one of the lowest reported area occupations and power consumptions. The quenching mechanism employed is based on a positive feedback loop that accelerates quenching right after sensing the avalanche current. We have employed a current starved inverter for the regulation of the hold-off time, which is more compact than other reported controllable delay implementations. This circuit has been fabricated in a standard 0.18 µm complementary metal-oxide-semiconductor (CMOS) technology. The SPAD has a quasi-circular shape of 12 µm diameter active area. The fill factor is about 11%. The measured time resolution of the detector is 187 ps. The photon-detection efficiency (PDE) at 540 nm wavelength is about 5% at an excess voltage of 900 mV. The break-down voltage is 10.3 V. A dark count rate of 19 kHz is measured at room temperature. Worst case post-layout simulations show a 117 ps quenching and 280 ps restoring times. The dead time can be accurately tuned from 5 to 500 ns. The pulse-width jitter is below 1.8 ns when dead time is set to 40 ns. Copyright © 2015 John Wiley & Sons, Ltd.
    No preview · Article · Jul 2015 · International Journal of Circuit Theory and Applications
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    ABSTRACT: The selection, modeling and characterization of Single Photon Avalanche Diodes (SPADs) are presented. Working with the standard 180nm UMC CMOS process, different SPAD structures are proposed in combination with several quenching circuits in order to compare their relative performances. Various configurations for the active region and the prevention of the premature edge breakdown are tested, looking for a miniaturization of the devices to implement image sensor arrays without loses in their performance.
    No preview · Conference Paper · Dec 2012
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    ABSTRACT: This book presents architectures, circuits, models, methods and practical considerations for the design of high-performance low-pass switched-capacitor (SC) sigma-delta A/D interfaces for mixed-signal CMOS ASICs. The main focus is on cascade architectures, although considerations pertaining to circuits and error analysis are general and hence valid for other architectures. It differs from other books in the complete, in-depth coverage of SC circuit errors. Another differentiating feature of this book is the coverage into a unified description of largely different application areas. It starts with a tutorial presentation of the fundamentals of low-pass sigma-delta modulators, their applications, and their most common architectures. This presentation is both complete and comprehensive. It then presents an exhaustive analysis of SC circuit errors with a twofold outcome. The book is completed with the detailed presentation of three high-performance modulator ICs: the first two are intended for DSL-like applications, whereas the third one is intended for automotive sensors.
    No preview · Article · Jan 2006
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    ABSTRACT: This paper presents design considerations for cascade Sigma-Delta Modulators (ΣΔMs) included in multi-standard wireless transceivers. Four different standards are covered: GSM, Bluetooth, UMTS and WLAN. A top-down design methodology is proposed to find out the optimum modulator architecture in terms of circuit complexity and reconfiguration parameters. The selected 2-1^(L-2) expandible YAM is high-level sized and several reconfiguration strategies are adopted at both architecture- and circuit-level in order to adapt the modulator performance to the different standards requirements with adaptive power consumption. Time-domain simulations are shown to validate the presented approach. This work has been supported by the Spanish Ministry of Science and Education (with support from the European Regional Development Fund) under contract ITEC2004-01752/MIC. Peer reviewed
    Full-text · Article · Jan 2006
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    ABSTRACT: Systematic Design of CMOS Switched-Current Bandpass Sigma-Delta Modulators for Digital Communication Chips gives a systematic methodology for designing ΣΔ Modulators (ΣΔMs), specially those of the bandpass type, realized in digital CMOS technologies by using switched-current (SI) circuits. For this purpose, an analysis of SI error mechanisms as well as their influence on the performance of ΣΔMs is presented in a detailed and comprehensive style. On the one hand, the depth of such an analysis allows designers to get practical knowledge of the performance degradation of SI ΣΔMs through closed-form expressions that relate the modulator specifications to SI cell design parameters. On the other hand, the behavioural models derived from that study make it possible a fast and precise time-domain simulation of SI ΣΔMs, shown in the book through a simulator developed in MATLAB/SIMULINK. The architectures and circuit design methodologies presented in this book are demonstrated through two standard CMOS IC prototypes - the first silicon realizations of SI bandpass ΣΔMs - intended for AM digital radio receivers. The good performance comparison obtained with current state-of-the-art of switched-capacitor ICs demonstrates the viability of SI circuits for the realization of digital communication chips. Systematic Design of CMOS Switched-Current Bandpass Sigma-Delta Modulators for Digital Communication Chips is organized such that it can be useful for a large audience: from novices in the field to experienced ΣΔM designers. The comprehensive treatment of SI ΣΔMs given in this book will allow all of them to improve their productivity through the incorporation of circuit knowledge and CAD tools to optimize the design and to shorten the design cycle. Peer reviewed
    No preview · Article · Jan 2002
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    ABSTRACT: This paper discusses the use of switched-current (SI) circuits to design Band-Pass ΣΔ Modulators (BP-ΣΔMs) suitable for AM digital radio receivers. First of all, the paper briefly outlines the concept and principles of BP-ΣΔMs, and introduces two modulator architectures which are obtained by applying a lowpass-to-bandpass transformation (i.e., z^-1 --> z^-2) to a first-order and a second-order Low-Pass ΣΔ Modulator (LP-ΣΔM), respectively. The resulting BP-ΣΔMs, respectively of second-order and of fourth-order, are then used as case studies for SI circuit implementation. Systematic analysis of the errors associated to SI circuits is carried out and models are presented to evaluate their incidence on the performance of BP-ΣΔMs; the significance of the different errors is illustrated via the two selected case studies. Fully-differential regulated-folded cascode SI memory cells are chosen to attenuate these errors. Based on the proposed error models, optimization is carried out to fulfill AM radio requirements in practical modulator implementations. Two IC prototypes have been fabricated in a CMOS technology, and measured, to validate the presented design methodology. One of these prototypes uses the fourth-order architecture to digitize AM signals, and features resolution with 60mW power consumption from a 5V supply voltage. The other uses the second-order architecture and features with 42mW in the commercial AM band, from 540kHz to 1600kHz. Experimental results show correct noise-shaping for sampling frequencies up to 16MHz, which means a significant operation frequency enhancement as compared to previously reported SI ΣΔ Modulators. Peer reviewed
    Full-text · Article · Dec 2001 · Microelectronics Journal
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    ABSTRACT: This paper presents a detailed study of the effect of the non-linear settling on the harmonic distortion of BandPass SD Modulators (BP-ΣΔMs) realized using Fully Differential (FD) SwItched-current (SI) circuits. Based on the analysis of building blocks, closed-form expressions are derived for the third-order intermodulation distortion of BP-ΣΔMs due to defective settling, on the one hand, and to the non-linearities of the sampling process, on the other. Time-domain simulations and measurements taken from a 0.8μm CMOS 4th-order BP-ΣΔM silicon prototype validate our approach. This work has been supported by the Spanish CICYT Project TIC 97-0580. Peer reviewed
    Full-text · Article · Jan 2001
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    ABSTRACT: This paper presents a detailed study on the transient response of SC integrators taking into account the effects of amplifier finite gain-bandwidth product and slew-rate during, unlike previous models, both the integration and sampling phases. Results are applied to the design of high-speed low-power SD modulators and simplified equations are obtained for manual-estimation of the settling error power. This work has been partially supported by the ESPRIT Project 29261 and the CICYT Project TIC 97-0580. Peer reviewed
    Full-text · Article · Jan 1999
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    José Manuel de la Rosa Utrera · Andreas Kaiser · Belén Pérez Verdú
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    ABSTRACT: A simulation tool named SDSI, specifically suited for the simulation of switched-current (SI) sigma-delta data converters, has been developed in an interactive design environment. The tool exploits the sampled-data nature of the circuits and provides several levels of hierarchy for the models. High level behavioural models are suited for initial system-level simulations and specification of building blocks. Lower level models, which take into account non-linear effects and eventually full SPICE level transistor models, are suited for bottom-up verification of circuits after the design of the building-blocks. There are no restrictions on the interoperability of both types of models. Very fast simulation times are achieved thanks to the sampled-data simulation approach, making the tool appropriate for the extensive analysis of sigma-delta modulators. The tool has been used to check the performance of a SI bandpass sigma-delta modulator fabricated in a 0.8μm CMOS technology. Experimental results validate this approach to the verification of SI sigma-delta modulators. This work has been partially supported by the Spanish CICYT Project TIC 97-0580. Peer reviewed
    Full-text · Article · Jan 1998
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    ABSTRACT: The principle of ΣΔ Modulation (ΣΔM) is extended in BPΣΔMs to bandpass signals, especially but not only, with a narrow bandwidth. Thus, BPΣΔMs have much in common with their lowpass counterparts - whose properties have been covered in previous Chapters of this book. However, there are some issues which are peculiar to BPΣΔ-ADCs. This Chapter is devoted to the description of these issues. In Section 11.2, digital radio receivers are revised, pointing out the necessity for an ADC at the IF location. Section 11.3 and Section 11.4 explain the basic concepts and architectural issues of BPΣΔ-ADCs. The problems derived from circuit implementation are treated in Section 11.5. Finally, Section 11.6 summarizes the performance of state-of-the-art BPΣΔ-ADCs. Peer reviewed
    Full-text · Article · Jan 1991
  • José L. Huertas · Belén Pérez‐Verdú · Angel Rodríguez‐Vázquez
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    ABSTRACT: This paper considers the design of self-limiting single-op-amp RC oscillators inside the frequency range where the slew rate is the dominant non-linearity. It is first demonstrated that limitation by the slew rate yields zero first-order frequency sensitivity with respect to changes in the op amp gain-bandwidth product (GB). Design procedures are then outlined for each of the structures comprising the complete set of canonical RC oscillators. Sensitivity figures providing criteria for comparison between the different structures are also included. Finally, experimental results are shown illustrating the validity of the proposed techniques.
    No preview · Article · Jan 1990 · International Journal of Circuit Theory and Applications
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    ABSTRACT: The RaMSiS Group (Radio And Mixed Signal Integrated Systems) of the Royal Institute of Technology Stockholm (KTH) and the Institute of Microelectronics of Seville (IMSE-CNM) of the Spanish Microelectronics Centre (CSIC).
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    ABSTRACT: We present a fourth-order bandpass ΣΔ switched-current modulator IC in 0.8 μm CMOS single-poly technology. It is the first reported integrated circuit realization of a bandpass ΣΔ modulator using switched-current circuits. Its architecture is obtained by applying a lowpass to bandpass transformation (z-1→ -z-2) to a second-order lowpass modulator. It has been realized using fully-differential circuitry with common-mode feedback. Measurements show 8 bit dynamic range up to 5MHz clock frequency. Peer reviewed
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    ABSTRACT: This paper presents a dual-quantization SC Sigma-Delta Modulator intended for A/D Conversion in ADSL applications. ESPRIT Project 29261 MIXMODEST. Peer reviewed
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    ABSTRACT: This paper discusses design considerations for cascade Sigma-Delta Modulators (ΣΔMs) included in multistandard wireless receivers. Four different standards are covered: GSM, Bluetooth, UMTS, and WLAN. A top-down design methodology is proposed to find out the optimum modulator architecture in terms of circuit complexity and reconfiguration parameters. Several reconfiguration strategies are adopted at both architecture- and circuit-level in order to adapt the modulator performance to the different standards requirements with adaptive power consumption. Time-domain behavioural simulations considering a 0.13μm CMOS implementation are shown to validate the presented approach. This work has been supported by the Spanish Ministry of Science and Education (with support from the European Regional Development Fund) under contract TEC2004-01752/MIC. Peer reviewed
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    ABSTRACT: EU ESPRIT Project 8795-AMFIS Peer reviewed
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    ABSTRACT: EU ESPRIT Project 8795-AMFIS Peer reviewed
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    ABSTRACT: This paper analyses the tonal behaviour of the quantization noise in second-order bandpass ΣΔ modulators. The analysis performed for lowpass modulators is extended to the bandpass case. As a result, closed form expressions for the frequency of idle tones are derived for different cases regarding the signal center frequency position. All these results have been validated by measurements from a silicon prototype using fully differential switched-current circuits implemented in a standard 0.8μm CMOS technology. This work has been supported by the Spanish CICYT Project TIC 97-0580. Peer reviewed
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    ABSTRACT: This chapter first presents a scalable MASH dual-quantization architecture and a companion optimum set of scaling coefficients which result into minimum resolution losses. The chapter then outlines the dominant circuit imperfections that degrade the operation of this architecture, and presents illustrative design exploration considerations induced by these circuit imperfections. Finally, some practical considerations pertaining to the implementation of an ADSL sigma-delta modulator in 0.25-μm CMOS technology are given and illustrated through experimental results.
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    ABSTRACT: The use of Sigma-Delta (ΣΔ) modulation for analog-to-digital conversion (ADC) in the communication frequency range is evaluated. Two high-order multi-bit architectures are proposed to achieve +12-bit dynamic range at 4Msample/s Nyquist rate using very low oversampling ratio. They show very low sensitivity to the internal D-to-A conversion (DAC) error with no calibration required. Simulations show that such performance can be achieved even in presence of circuit imperfections. This work has been partially supported by the Spanish CICYT Project TIC 97-0580. Peer reviewed
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