P. D. Ye

Purdue University, ウェストラファイエット, Indiana, United States

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Publications (250)668.49 Total impact

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    ABSTRACT: Few layer black phosphorus has emerged as a strong candidate owing to its high carrier mobility with most of the previous research work focused on its p-type properties. Very few work has been done on its n-type electronic characteristics which is important not only for the complementary operation for logic, but also crucial for understanding the carrier transport through the metal-black phosphorus junction. A thorough understanding and proper evaluation on the performance potential of both p- and n-types are highly desirable. In this paper, we investigate the temperature dependent ambipolar operation of both electron and hole transport from 300 K to 20 K. On-currents as high as 85 μA/μm for a 0.2 μm channel length BP nFET at 300 K is observed. Moreover, we provide the first systematically studied on the low frequency noise mechanisms for both n-channel and p-channel BP transistors. The dominated noise mechanism of few-layer BP nFET and pFET are mobility fluctuation and carrier number fluctuations with correlated mobility fluctuations, respectively. We have also established baseline of the low electrical noise of 8.1×10-9 μm2 Hz-1 at 10 Hz at room temperature for BP pFET, which is 3 times of improvement over previous reports, and 7.0×10-8 μm2 Hz-1 for BP nFET for the first time.
    No preview · Article · Jan 2016 · Nanoscale
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    ABSTRACT: Magnetoresistance, the modulation of resistance by magnetic fields, has been adopted and continues to evolve in many device applications including hard-disk, memory and sensors. Magnetoresistance in non-magnetic semiconductors has recently raised much attention and shows great potential due to its large magnitude that is comparable or even larger than magnetic materials. However, most of the previous work focus on two terminal devices with large dimensions, typically of micrometer scales, which severely limit their performance potential and more importantly, scalability in commercial applications. Here, we investigate magnetoresistance in the impact ionization region in InGaAs nanowires with 20 nm diameter and 40 nm gate length. The deeply scaled dimensions of these nanowires enable high sensibility with less power consumption. Moreover, in these three terminal devices, the magnitude of magnetoresistance can be tuned by the transverse electric field controlled by gate voltage. Large magnetoresistance between 100 percent at room temperature and 2000 percent at 4.3 K can be achieved at 2.5 T. These nanoscale devices with large magnetoresistance offer excellent opportunity for future high density large scale magneto-electric devices using top-down fabrication approaches, which are compatible with commercial silicon platform.
    No preview · Article · Nov 2015 · Nano Letters
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    ABSTRACT: In this paper, we report the observation of random telegraph noise (RTN) in highly scaled InGaAs gate-all-around (GAA) MOSFETs fabricated by a top-down approach. RTN and low-frequency noise were systematically studied for devices with various gate dielectrics, channel lengths, and nanowire diameters. Mobility fluctuation is identified to be the source of 1/f noise. The 1/f noise was found to decrease as the channel length scaled down from 80 to 20 nm comparing with classical theory, indicating the near-ballistic transport in highly scaled InGaAs GAA MOSFET. Low-frequency noise in ballistic transistors is discussed theoretically.
    No preview · Article · Nov 2015 · IEEE Transactions on Electron Devices
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    ABSTRACT: The interfacial chemistry between the “half cycle” atomic layer deposited (ALD) Al2O3 and black phosphorus (black-P) was examined using in situ X-ray photoelectron spectroscopy (XPS). Two samples, native and freshly exfoliated, are investigated to understand the effect of oxidation on the initial ALD nucleation. It is found that annealing samples in the ALD chamber results in an increase of oxidation, caused most likely by oxygen transferring from surface adventitious contamination. After the half cycle ALD process, the P-oxide concentration increases, indicating interface deterioration during the Al2O3 deposition. Based on the Al2O3 nucleation or growth behavior observed in the half cycle ALD studies, a true ALD growth tends to occur only after formation of a complete monolayer of oxide on the clean black-P surface with minimum oxidation concentration.
    No preview · Article · Nov 2015 · Microelectronic Engineering
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    ABSTRACT: 2D transition metal dichalcogenides (TMDCs) are nanomanufactured using a generalized strategy with self-assembled DNA nanotubes. DNA nanotubes of various lengths serve as lithographic etch masks for the dry etching of TMDCs. The nanostructured TMDCs are studied by atomic force microscopy, photoluminescence, and Raman spectroscopy. This parallel approach can be used to manufacture 2D TMDC nanostructures of arbitrary geometries with molecular-scale precision. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.
    No preview · Article · Aug 2015 · Small

  • No preview · Conference Paper · Jun 2015
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    ABSTRACT: In situ "half cycle" atomic layer deposition (ALD) of Al2O3 was carried out on black phosphorus ("black-P") surfaces with intentionally modifying the phosphorus oxide concentrations. X-ray photoelectron spectroscopy is employed to investigate the interfacial chemistry and the nucleation of the Al2O3 on black-P surfaces. This work suggests that exposing a sample that is initially free of phosphorus oxide to the ALD precursors does not result in detectable oxidation. However, when the phosphorus oxide is formed on the surface prior to deposition, the black-P can react with both the surface adventitious oxygen contamination and the H2O precursor at the deposition temperature of 200 C. As a result, the concentration of the phosphorus oxide increases after both annealing and the atomic layer deposition process. The nucleation rate of Al2O3 on black-P is correlated with the amount of oxygen on samples prior to the deposition. The growth of Al2O3 follows a "substrate inhibited growth" behavior where an incubation period is required. Ex situ atomic force microscopy is also used to investigate the deposited Al2O3 morphologies on black-P where the Al2O3 tends to form islands on the exfoliated black-P samples. Therefore, surface functionalization may be needed to get a conformal coverage of Al2O3 on the phosphorus oxide free samples.
    No preview · Article · May 2015 · ACS Applied Materials & Interfaces
  • M. Si · S. Shin · N.J. Conrad · J. Gu · J. Zhang · M.A. Alam · P.D. Ye
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    ABSTRACT: InGaAs is a promising channel material for high performance CMOS logic circuits due to its large electron injection velocity. InGaAs Gate-All-Around (GAA) MOSFETs have been demonstrated; these transistors offer large drive current and excellent immunity to short channel effects (SCE). However, the characterization and reliability of InGaAs GAA MOSFETs are still challenging. In this paper, we (i) discuss the challenges and new characterization methodologies to evaluate Dit, Rsd and other parameters on short channel InGaAs GAA MOSFETs, (ii) discuss device characterization based on low frequency noise and RTN, (iii) image the complexity of heat dissipation by using newly developed thermoreflectance method, and (iv) review the current research on 3D InGaAs MOSFET reliability including PBTI, HCI, and gate dielectric breakdown.
    No preview · Article · May 2015
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    ABSTRACT: A novel recessed channel and source/drain (S/D) technique is employed in Ge nMOSFETs, which greatly improves metal contacts to n-type Ge with contact resistance of down to 0.23 $Omega cdot {rm mm}$ and enhances gate electrostatic control with $I_{rm ON} / I_{rm OFF}$ of $> 10^{5}$ . The recessed S/D contacts are thoroughly investigated, showing strong dependence on the doping profile. For the first time, the drain current of Ge nMOSFETs has exceeded 1 A/mm with an $I_{d}$ of 1043 mA/mm on a 40-nm $L_{rm ch}$ device. Scalability study is carried out in deep sub-100-nm region on Ge nMOSFETs with $L_{rm ch}$ down to 25 nm. Interface study is also conducted with a new postoxidation method introduced, which significantly reduces the interface trap density. Device behaviors corresponding to interface traps are also investigated through a Technology Computer Aided Design simulation.
    No preview · Article · May 2015 · IEEE Transactions on Electron Devices
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    ABSTRACT: High-performance 0.1- $mu text{m}$ InAlN/GaN high electron-mobility transistors (HEMTs) have been successfully developed for power amplifiers operating at E-band (targeting 71–76 and 81–86-GHz bands). High maximum drain current of 1.75 A/mm and maximum extrinsic transconductance of 0.8 S/mm have been achieved for depletion-mode devices. Enhancement-mode HEMTs have also shown maximum drain current of 1.5 A/mm and maximum extrinsic transconductance of 1 S/mm. The selection of atomic layer deposition aluminum oxide (Al2O3) for device passivation enables a two-terminal breakdown voltage of $sim 25$ V, excellent subthreshold characteristics as well as the pulsed-IV featuring little current collapse for both types of HEMTs. When biased at a drain voltage of 10 V, a first-pass two-stage power amplifier design based on 0.1- $mu text{m}$ depletion-mode devices has demonstrated an output power of 1.43 W with 12.7% power-added efficiency at 86 GHz, a level of performance that has been attained previously only by state-of-the-art counterparts based on AlGaN/GaN HEMTs at a much higher drain bias and compression level.
    No preview · Article · May 2015 · IEEE Electron Device Letters
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    ABSTRACT: The metal contacts on 2D black phosphorus field-effect transistor and photodetectors are studied. The metal work functions can significantly impact the Schottky barrier at the metal-semiconductor contact in black phosphorus devices. Higher metal work functions lead to larger output hole currents in p-type transistors, while ambipolar characteristics can be observed with lower work function metals. Photodetectors with record high photoresponsivity (223 mA/W) are demonstrated on black phosphorus through contact-engineering.
    Full-text · Article · Mar 2015 · Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International
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    ABSTRACT: Black phosphorus has been revisited recently as a new two-dimensional material showing potential applications in electronics and optoelectronics. Here we report, for the first time, the anisotropic in-plane thermal conductivity of suspended few-layer black phosphorus measured by micro-Raman spectroscopy. The armchair and zigzag thermal conductivities ($k_{armchair}$ and $k_{zigzag}$) are ~20 W/mK and ~40 W/mK for black phosphorus films thicker than 15 nm, respectively, and decrease to ~10 W/mK and ~20 W/mK as the film thickness is reduced, exhibiting significant anisotropy of in-plane thermal transport and strong surface scattering of acoustic phonons. The thermal conductivity anisotropic ratio $k_{zigzag}/k_{armchair}$ is found to be ~2 for thick black phosphorus films and drops to ~1.5 for the thinnest 9.5-nm-thick film. First-principles modeling of few-layer black phosphorus reveals that the observed anisotropy is primarily related to the asymmetric phonon dispersion, whereas the intrinsic phonon scattering rates are found to be similar along the armchair and zigzag directions. Surface scattering in the black phosphorus films is shown to strongly suppress the contribution of long-mean-free-path acoustic phonons.
    Full-text · Article · Mar 2015 · Nature Communications
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    ABSTRACT: Thermal characterization of high-speed switching power transistors, such as high electron mobility transistors (HEMT), is critical for the evaluation of their performance as well as their long-term reliability. Unlike IR thermal imaging, thermoreflectance thermal imaging (TRI) uses LED lights in the visible range and therefore can be used to measure thermal response of these nanoscale devices under operating condition. However, TRI is also limited in terms of spatial resolution by optical diffraction as we reach device sizes on the order of hundreds of nanometer. We carried out a series of thermoreflectance thermal imaging experiments on the metal heater lines with widths ranging from 100 nm to 1 µm fabricated on InGaAs semiconductor film. Analytical and finite element numerical modeling are used to compare experimental data with theoretical temperature profiles. We demonstrate that thermoreflectance thermal imaging is capable of detecting temperature rise in devices with sub-diffraction feature sizes. We show that optical diffraction leads to underestimation of the magnitude of small scale hot spots. We also present a combined analytical-numerical model to reproduce the experimental results, and finally propose an approach that can be utilized to compensate for this diffraction artifact and acquire the correct temperature response from thermoreflectance thermal imaging results.
    Full-text · Conference Paper · Mar 2015
  • N. Conrad · M. Si · S.H. Shin · J.J. Gu · J. Zhang · M.A. Alam · P.D. Ye
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    ABSTRACT: In this work, we report the first observation of RTN in highly scaled InGaAs GAA MOSFETs fabricated by a top-down approach. RTN and low frequency noise were systematically studied for devices with various gate dielectrics, channel lengths and nanowire diameters. Mobility fluctuation is confirmed to be the source of low-frequency noise, showing 1/f characteristics. Low-frequency noise was found to decrease as the channel length scaled down from 80 nm to 20 nm, indicating the near-ballistic transport in highly scaled InGaAs GAA MOSFET.
    No preview · Article · Feb 2015
  • Heng Wu · Nathan Conrad · Wei Luo · Peide D. Ye
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    ABSTRACT: We report the first experimental demonstration of Ge CMOS circuits, based on a novel recessed channel and S/D technique. Aggressively scaled non-Si CMOS logic devices with channel lengths (Lch) from 500 to 20 nm, channel thicknesses (Tch) of 25 and 15 nm, EOTs of 4.5 and 3 nm and a small width ratio (Wn:Wp=1.2) are realized on a Ge-on-insulator (GeOI) substrate. The CMOS inverters have high voltage gain of up to 36 V/V, which is the best value among all of the non-Si CMOS results by the standard top-down approach. Scalability studies on Ge CMOS inverters down to 20 nm are carried out for the first time. NAND and NOR logic gates are also investigated.
    No preview · Article · Feb 2015 · Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International
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    ABSTRACT: Gate-all-around MOSFETs use multiple nanowires to achieve target ION, along with excellent 3D electrostatic control of the channel. Although self-heating effect (SHE) has been a persistent concern, the existing characterization methods, based on indirect measure of mobility and specialized test structures, do not offer adequate spatio-temporal resolution. In this paper, we develop an ultra-fast, high resolution thermo-reflectance (TR) imaging technique to (i) directly observe the increase in local surface temperature of the GAA-FET with different number of nanowires (NWs), (ii) characterize/interpret the time constants of heating and cooling through high resolution transient measurements, (iii) identify critical paths for heat dissipation, and (iv) detect in-situ time-dependent breakdown of individual NW. Our approach also allows indirect imaging of quasi-ballistic transport and corresponding drain/source asymmetry of self-heating. Combined with the complementary approaches that probe the internal temperature of the NW, the TR-images offer a high resolution map of self-heating in the surround-gate devices with unprecedented precision, necessary for validation of electro-thermal models and optimization of devices and circuits.
    No preview · Article · Feb 2015 · Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International
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    ABSTRACT: Inversion-mode GaAs wave-shaped metal-oxide-semiconductor field-effect transistors (WaveFETs) are demonstrated using atomic-layer epitaxy of La2O3 as gate dielectric on (111)A nano-facets formed on a GaAs (100) substrate. The wave-shaped nano-facets, which are desirable for the device on-state and off-state performance, are realized by lithographic patterning and anisotropic wet etching with optimized geometry. A well-behaved 1 μm gate length GaAs WaveFET shows a maximum drain current of 64 mA/mm, a subthreshold swing of 135 mV/dec, and an ION/IOFF ratio of greater than 107.
    No preview · Article · Feb 2015 · Applied Physics Letters
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    ABSTRACT: We demonstrate a single-step, laser-based technique to fabricate silicon nanowire field effect transistors. Boron-doped silicon nanowires are synthesized using a laser-direct-write chemical vapor deposition process, which can produce nanowires as small as 60 nm, far below the diffraction limit of the laser wavelength of 395 nm. In addition, the method has the advantages of in situ doping, catalyst-free growth, and precise control of nanowire position, orientation, and length. Silicon nanowires are directly fabricated on an insulating surface and ready for subsequent device fabrication without the need for transfer and alignment, thus greatly simplifying device fabrication processes. Schottky barrier nanowire field effect transistors with a back-gate configuration are fabricated from the laser-direct-written Si nanowires and electrically characterized.
    No preview · Article · Feb 2015 · Nanotechnology
  • Sichao Li · Lin Dong · Xuefei Li · Peide Ye · Yanqing Wu
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    ABSTRACT: The interface between III-V and gate dielectrics is a key challenge in developing high performance III-V MOSFETs such as GaAs and InGaAs. The high density of interface states (Dit) makes it very difficult to modulate surface Fermi level and inversion carrier concentration. By growing an epitaxial layer (ALE) of La2O3 dielectric on GaAs(111)A, Dit can be effectively reduced and Fermi levels movement efficiency is greatly improved. In this paper, we studied systematically the carrier transport including IV, CV and conductance method at temperatures ranging from 300 K to low temperatures down to 4.3 K.
    No preview · Article · Jan 2015
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    ABSTRACT: High performance-scaled MoS2 transistors down to 100 nm are studied at various temperatures down to 20 K, where highest drive current of 800 μA μm(-1) can be achieved. Extremely low electrical noise of 2.8 × 10(-10) μm(2) Hz(-1) at 10 Hz is also achieved at room temperature. Furthermore, negative differential resistance behavior is experimentally observed and its origin of self-heating is identified using pulsed-current-voltage measurements. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.
    No preview · Article · Jan 2015 · Advanced Materials

Publication Stats

6k Citations
668.49 Total Impact Points


  • 2005-2015
    • Purdue University
      • • School of Electrical and Computer Engineering
      • • Department of Electrical and Computer Engineering Technology (ECET)
      ウェストラファイエット, Indiana, United States
    • Lehigh University
      Bethlehem, Pennsylvania, United States
  • 2014
    • Michigan State University
      • Department of Physics and Astronomy
      Ист-Лансинг, Michigan, United States
  • 2012
    • Center for Responsible Nanotechnology
      Menlo Park, California, United States
  • 2001-2006
    • Princeton University
      • Department of Electrical Engineering
      Princeton, New Jersey, United States
  • 2002-2004
    • Florida State University
      • Department of Physics
      Tallahassee, Florida, United States
    • National High Magnetic Field Laboratory
      Tallahassee, Florida, United States