Desheng Chen

Feng Chia University, 臺中市, Taiwan, Taiwan

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Publications (2)0 Total impact

  • [Show abstract] [Hide abstract]
    ABSTRACT: An application-specific instruction-set processor (ASIP) is a technique that exploits special characteristics of application(s) to meet the desired performance, cost and power requirements. The generation and selection of Application-Specific Instructions (ASIs) dramatically affect the quality of an ASIP with design constraints such as number of register file I/Os and hardware cost. In this paper, a design flow is developed to automatically combine the disjoint operations as an ASI to enrich the selection varieties. The operation cover-ratio and the ASI latency model are used to select profitable ASIs so that the performance can be improved. The experimental results show the maximal 1.64x speed up can be obtained under hardware cost less than 8000 LEs in Altera FPGA.
    No preview · Conference Paper · Aug 2008
  • Jiying Wu · Chijie Lin · Desheng Chen · Yiwen Wang
    [Show abstract] [Hide abstract]
    ABSTRACT: To optimize system performance for a specific target application, embedded system designers may add some new instructions, called application-specific instructions (ASIs), by automatic design flow. In past days, most application-specific instruction-set processor (ASIP) researches focus on reducing instruction latency to improve performance regardless of the impact of memory access. In this paper, a design flow is proposed to automatically generate ASIs and to compare the performance between considering register transferring and regardless of it. The experiment results show the proposed approach can achieve up to 14% performance improvement and 10% memory access reduction comparing to no register transferring consideration.
    No preview · Conference Paper · Aug 2008