Jae-Seung Lee

Pohang University of Science and Technology, Geijitsu, Gyeongsangbuk-do, South Korea

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Publications (11)9.72 Total impact

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    ABSTRACT: A mutual-capacitive touch-sensor read-out integrated circuit (ROIC) with a differential sensing scheme is proposed to reduce the driving pulse amplitude of touch sensor panel (TSP) down to 0.4 V. This reduction is achieved by mitigating the effect of the liquid crystal display (LCD) common-voltage (VCOM) noise, which is time periodic. To accomplish this mitigation, the TSP driving pulse (VSTM) is synchronized to the gate-driver-pulse generating signal (GCLK) of LCD, and its frequency is set to ( $2n+1$ ) times the frequency of GCLK, where $n$ is a non-negative integer. The repetition period $T_{rm N}$ of the VCOM noise is one half of the GCLK period. A receiver channel consists of a charge amplifier, a chopper, and an integrator; all are in differential circuits. The chopper is driven by the VSTM. The integration period of the integrator is set to $2T_{rm N}$ to suppress the periodic LCD noise. A referenceless clock and data recovery circuit are used to generate VSTM from GCLK continuously with time in spite of the discontinuity of GCLK during the vertical blanking period. The proposed ROIC fabricated in a 0.35- $mu text{m}$ CMOS was applied to a 6.9 in $12times 16$ TSP located on a rather noisy 23 in in-plane switching LCD monitor. The measured signal-to-noise ratio changes from 27 to 9 dB as the VSTM amplitude changes from 3.3 to 0.4 V, where the GCLK frequency is 16.8 kHz and the VSTM frequency is 352.8 kHz. The reporting rate of the ROIC is 175 Hz.
    No preview · Article · Aug 2015 · IEEE Sensors Journal
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    ABSTRACT: Analysis of an open-loop time amplifier shows good agreement between measurements and calculations on the time gain, distortion of time gain, and rms noise and offset of output time difference. The time amplifier is based on the slew rate control method. It achieves a large time gain up to 120 and a wide range of input time difference up to 2 ns. The circuit consists of two precharged capacitors and current sources, where one capacitor is discharged at a fast slew rate during the time interval of the input time difference and then both capacitors are discharged at the same slow slew rate. The time gain is simply determined by the ratio of two bias current values. The proposed time amplifier is followed by an 8-bit TDC to obtain the digital output code. The time gain distortion caused by channel length modulation is less than 1.6% for the input time difference larger than 100 ps. The time offset and the rms noise of output time difference are inversely proportional to the smaller bias current. The rms noise is dominated by the noise of the comparator reference voltage. The time amplifier and TDC consume 0.36 mW and 1 mW, respectively, at 1.2 V supply in a 0.13 $muhbox{m}$ CMOS process.
    No preview · Article · Jul 2014 · Circuits and Systems II: Express Briefs, IEEE Transactions on
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    ABSTRACT: The time-periodic property of the LCD VCOM noise is utilized to reduce the effect of the VCOM noise on the mutual-capacitance measuring touch sensor placed on a LCD panel. The amplitude of the touch sensor driving signal (VSTM) can be reduced reliably down to 0.4 V with the reporting rate of 189 Hz, by using the following two methods. (1) The frequency of VSTM is set to (n+0.5)·fN, by synchronizing VSTM to a LCD gate driver signal with a referenceless CDR. fN is the inverse of the LCD VCOM noise period (TN) and n is a positive integer. (2) The reset period of the RX integrator is set to 2·TN.
    No preview · Conference Paper · Jun 2014
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    ABSTRACT: A 3.8 Gb/s multi-drop single-ended integrating DFE (IDFE) receiver is implemented in a 0.18 um CMOS by using a single-loop LMS-algorithm to find the DFE coefficients automatically. Initially, a preamble input data pattern ('1101') is applied to the main IDFE circuit to determine the DFE coefficients, while a fixed input data pattern ('1111') is applied to the replica IDFE circuit. The difference between the outputs of the two IDFE circuits is used in the feedback loop to determine the DFE coefficients. The reference voltage (Vref) of preamplifier is generated inside chip by a Vref loop to reduce the effect of the external noise and the input offset voltage of preamplifier and IDFE circuits and also to track the mid-level of the input data swing in spite of process variations of TX chips. An integrating deskew scheme with a minimum overhead is introduced. 2-drop and 4-drop DRAM channels are tested. The maximum data rate was increased from 1.0 Gb/s to 2.6 Gb/s by DFE in the heavily loaded 4-drop interface, from 3.5 Gb/s to 3.8 Gb/s by DFE in the 2-drop interface.
    No preview · Article · Oct 2011 · IEEE Journal of Solid-State Circuits
  • Hye-Jung Kwon · Jae-seung Lee · Jae-Yoon Sim · Hong-June Park
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    ABSTRACT: Recently, time amplifiers are used in time-to-digital converters(TDC) because the time resolution is better than the voltage resolution in modern integrated circuits. However, the conventional time amplifiers are limited in their time gain and input time difference range, because of their positive-feedback closed-loop architecture. An open-loop time amplifier is proposed in this work to achieve a large time gain up to 120 and a wide range of input time difference(10ps∼2ns). Besides, the time gain is the same as the current bias ratio. The worst-case average gain error which shows linear characteristics of the time amplifier is smaller than 5.3% The proposed time amplifier was successfully used in the monitoring circuit for threshold voltage variations of NMOS and PMOS FETs. The monitoring circuit consists of VCDL, time amplifier and TDC. The circuit was implemented by 0.13μm CMOS process.
    No preview · Article · Jan 2011
  • Jae-seung Lee · Jae-Yoon Sim · Hong-June Park
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    ABSTRACT: A high-throughput on-chip monitoring circuit with a digital output is proposed for the variations of the NMOS and PMOS threshold voltages. A voltage-controlled delay line (VCDL) and a time-to-digital converter (TDC) are used to convert a small difference in analog voltage into a large difference in time delay. This circuit was applied to the transistors of W = 10µm and L = 0.18µm in a 16 × 16 array matrix fabricated with a 0.18-µm process. The measurement of the threshold voltage shows that the maximum peak-to-peak intra-chip variation of NMOS and PMOS transistors are about 31.7mV and 32.2mV, respectively, for the temperature range from -25°C to 75°C. The voltage resolutions of NMOS and PMOS transistors are measured to be 1.10mV/bit and 3.53mV/bit at 25°C, respectively. The 8-bit digital code is generated for the threshold voltage of a transistor in every 125ns, which corresponds to the 8-MHz throughput.
    No preview · Article · Aug 2010 · IEICE Transactions on Electronics
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    ABSTRACT: A 2-Gb/s integrating decision-feedback equalization (DFE) receiver was implemented for a four-drop single-ended DRAM interface channel by using a 0.25- mum CMOS process. The receiver combines both DFE and integration operations in a single receiver circuit so that the DFE operation reduces the intersymbol interference and the integration operation reduces the high-frequency noise. The DFE operation was implemented by switching the capacitance values of the two output nodes of a differential integrator, depending on the previous decision data. A look-ahead scheme was used to reduce the DFE loop delay. A MUX-embedded D flip-flop was used in the look-ahead circuit to further reduce the DFE loop delay and latency. The DFE operation enhanced the voltage margins by 110% and 90% at the 2-Gb/s stubless channel and the 1.2-Gb/s stub series terminated logic channel, respectively. The chip area and the power dissipation of the proposed receiver chip were 220 times 120 mum<sup>2</sup> and 10 mW, respectively, at the data rate of 2 Gb/s.
    No preview · Article · Sep 2009 · Circuits and Systems I: Regular Papers, IEEE Transactions on
  • Source
    Jae-Seung Lee · Jae-Yoon Sim · Hong June Park
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    ABSTRACT: A systematic design guide for 3-stage CMOS operational amplifier (op amp) with nested Gm-C frequency compensation (NGCC) was proposed. With the given specification such as gain-bandwidth (GB), the ratio of high frequency pole to GB, phase margin, input common-mode range, and load capacitance, the guide generates the design parameters that minimize total area or current. The test chip designed by the proposed guide was fabricated with a 0.18-mum CMOS process. The simulation results show reasonable performances with 1.2-V supply voltage, and the measurement results show low-voltage operations of the designed op amps with 0.6-V supply voltage.
    Preview · Conference Paper · Dec 2008
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    ABSTRACT: A 3.2Gb/s single-ended current-integrating DFE receiver with 8b parallel data for 2-drop DRAM interface is implemented in a 0.18mum CMOS process. The reference voltage for the receiver is generated internally to reduce the external coupling noise. A single-loop implementation of sign-sign LMS algorithm is used to decide the single-tap equalization coefficient of the DFE receiver instead of the previous dual-loop implementation.
    No preview · Conference Paper · Mar 2008
  • Source
    Hyung-Joon Chi · Jae-Seung Lee · Jae-Yoon Sim · Hong-June Park
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    ABSTRACT: A DLL-based clock generator with the capability of multiplied four phase clock generation was designed using a 0.18um CMOS process. An adaptive bandwidth DLL with a regulated supply delay line was used for a multiphase clock generation and a low jitter. An extra phase detector (PD) in a reference DLL solves the problem of the initial VCDL delay and achieves a fast lock time. Twice multiplied four phase clocks were generated at the outputs of four edge combiners, where the timing alignment was achieved using a coarse lock signal and the 10 multiphase clocks with T/8 time difference. Those four clocks were combined one more time using a static XOR circuit. Therefore the four times multiplication was achieved. With a 1.8V supply, the rms jitter of 2.1ps and the peak-to-peak jitter of 14.4ps were measured at 1.25GHz output. The operating range is . It consumes 57mW and occupies 450*325um2 of die area.
    Preview · Article · Jan 2006 · Journal of Semiconductor Technology and Science
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    ABSTRACT: An analytic design guide was formulated for the design of 3-stage CMOS OP amp with the nested Gm-C(NGCC) frequency compensation. The proposed design guide generates straight-forwardly the design parameters such as the W/L ratio and current of each transistor from the given design specifications, such as, gain-bandwidth, phase margin, the ratio of compensation capacitance to load capacitance. The applications of this design guide to the two cases of 10pF and 100pF load capacitances, shows that the designed OP amp work with a reasonable performance in both cases, for the range of compensation capacitance from 10% to 100% of load capacitance.
    Full-text · Article · Jan 2006 · Journal of Semiconductor Technology and Science

Publication Stats

39 Citations
9.72 Total Impact Points


  • 2006-2015
    • Pohang University of Science and Technology
      • • Department of Electronic and Electrical Engineering
      • • Department of Electrical and Computer Engineering
      Geijitsu, Gyeongsangbuk-do, South Korea