[Show abstract][Hide abstract] ABSTRACT: A 1/2.7-in 1944 times 1484 pixel CMOS image sensor with double CDS architecture fabricated in a 0.18-mum single-poly triple-metal (1P3M) CMOS process is described. It operates at 48 MHz in a progressive scanning mode at 60 frames/s for full high-definition (HD) imaging. Two transistors/pixel architecture and low optical stack with double microlenses achieve 14.6 ke macr/1times ldr s sensitivity and 14 ke macr saturation. Double CDS architecture with a high-gain column amplifier realized a low noise floor of 3.5 e macr<sub>rms</sub>. Optimized shallow-trench isolation achieved very low dark current of 12.2 e macr/s (60degC). This image sensor also realizes low power consumption of 220 mW.
No preview · Article · Jan 2008 · IEEE Journal of Solid-State Circuits
[Show abstract][Hide abstract] ABSTRACT: A 1/2.7 inch 1944times1092pixels CMOS image sensor with multi-gain column amplifier and double noise canceller is fabricated in a 0.18mum 1P3M CMOS process. It operates at 48MHz in a progressive scanning mode at 60fps. A 2T/pixel architecture and low optical stack with micro innerlens achieve 14.8ke<sup>-</sup>/1x-s sensitivity, 14ke<sup>-</sup> saturation, 3.7e<sup>-</sup> <sub>rms</sub> noise and 12.2e<sup>-</sup> dark current at 60degC.