Chung-Chih Hung

National Chiao Tung University, Hsin-chu-hsien, Taiwan, Taiwan

Are you Chung-Chih Hung?

Claim your profile

Publications (68)30.32 Total impact

  • Zong-Yi Chen · Chung-Chih Hung
    [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents a power-efficient realization of a third-order continuous-time delta-sigma (CT−∆ Σ) modulator with 3-bit time-domain flash quantizer (TDFQ) and data-weighted averaging (DWA) based on the shifter output and input. Using the time-domain quantizer can overcome design issues in low voltage supply during CMOS downscaling. The CT−∆ Σ modulator uses the TDFQ instead of a voltage-domain quantizer to reduce power consumption. The proposed TDFQ solves the linearity problem of the delay-based voltage-to-time converter (VTC) without calibration circuit while also increasing the quantizer input range and saving energy. Moreover, in order to reduce the mismatch effects of a multibit DAC and achieve low power consumption, implementation of a low-power DWA circuit is proposed without using a digital adder to calculate pointer for controlling barrel shift circuit. This chip was fabricated in CMOS 90 nm process. The proposed CT−∆ Σ modulator consumes 5.8 mW from 1.0 V and achieves peak SNDR of 65.3 dB over the 20 MHz bandwidth, which results in FOM_W = 96.3 fJ/level and FOM_S = 161 dB.
    No preview · Article · Dec 2015 · IEEE Journal on Emerging and Selected Topics in Circuits and Systems
  • Zhe-Yang Huang · Chun-Chieh Chen · Chung-Chih Hung
    [Show abstract] [Hide abstract]
    ABSTRACT: A low-power voltage-controlled oscillator (VCO) with voltage-controlled inductor for V-band wireless personal area network communication systems is presented in this study. The proposed VCO with a voltage-controlled inductor provides a centre frequency of 45.62 GHz and was implemented in a 90 nm RF-CMOS process. A tuning range of 1.28 GHz (44.98-46.26 GHz) with maximum control voltage of 1.0 V can be achieved. The phase noise is -92.8 dBc/Hz at 1 MHz offset frequency. The VCO core consumes 5.8 mW through a 1.0 V supply voltage and the active area is 0.13 mm2. The calculated figure-of-merit is -178.3.
    No preview · Article · Aug 2015 · IET Microwaves Antennas & Propagation
  • Source
    Zhe-Yang Huang · Chun-Chieh Chen · Chung-Chih Hung
    [Show abstract] [Hide abstract]
    ABSTRACT: A 65–77 GHz low power, meander-type transmission line CMOS low-noise amplifier for E-band millimetre-wave communication using 90 nm MS/RF CMOS process is demonstrated. The low-noise amplifier consists of multi-stage cascaded common-source amplifiers with optimized noise figure, power gain, and power consumption. The LNA achieves 11.7 dB power gain, 5.5 dB noise figure, and 17.7 mW power consumption. The meander-type transmission line circuit design is adopted to reduce chip area; the total transmission line area in LNA is only 0.024 mm2.
    Preview · Article · Jul 2015 · IEICE Electronics Express
  • Source
    Zhe-Yang Huang · Chun-Chieh Chen · Chung-Chih Hung
    [Show abstract] [Hide abstract]
    ABSTRACT: A differential VCO with differential push-push frequency doubler for dual-band application is proposed. The dual-band VCO (DB-VCO) adopts the tunable -Gm to optimize the wide tuning start-up condition. The proposed DB-VCO was implemented in 180-nm CMOS process. The DB-VCO provides a fundamental center frequency at 4.476 GHz and a double frequency at 8.985 GHz. A tuning range of fundamental frequency is 1.125 GHz (3.928 GHz - 5.053 GHz), and a tuning range of the double frequency is 2.257 GHz (7.856 GHz - 10.113 GHz) with maximum control voltage of 1.0 V can be achieved. The phase noise is -96.0 dBc/Hz at 1MHz offset from center of the DB-VCO fundamental frequency. And the phase noise is -86.4 dBc/Hz at 1MHz offset from center of the DB-VCO double frequency. The power dissipation of the DB-VCO core is 6.6 mW through 1.0 V supply voltage. The active area is 0.09mm2.
    Preview · Article · Mar 2015 · IEICE Electronics Express
  • Zhe-Yang Huang · Chun-Chieh Chen · Chung-Chih Hung
    [Show abstract] [Hide abstract]
    ABSTRACT: A low-noise amplifier (LNA) with cascode structure and shunt-peaking load is presented in this article. Both Narrow-band input impedance and wide-band input impedance LNAs were implemented in 0.18 μm CMOS process. Maximum power gain of the narrow-band input impedance LNA is 19.3 dB; maximum power gain of the wide-band input impedance LNA is 15.3 dB. Minimum noise figure of the narrow-band input impedance LNA is 3.1 dB; minimum noise figure of the wide-band input impedance LNA is 3.0 dB. Power consumptions including buffers are 24.5 and 25.6 mW, respectively.
    No preview · Article · Feb 2015 · Journal- Chinese Institute of Engineers
  • Fang-Ting Chou · Chung-Chih Hung

    No preview · Article · Jan 2015 · IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • Fang-Ting Chou · Chung-Chih Hung
    [Show abstract] [Hide abstract]
    ABSTRACT: A compact and low-power design of a 12-bit binary-weighted current-steering DAC is presented. Instead of 4096 unit current cells, the proposed design uses 192 unit current sources with two reference currents. The silicon area of the generation circuit of two reference currents is very compact as well. The area of the total current source arrays is smaller than four times the area of 6-bit current source arrays, which has significantly reduced the dimension of the analog part of a conventional 12-bit DAC. The proposed DAC achieves 400 MS/s update rate and consumes 38.7 mW from single 1.8 V supply.
    No preview · Article · Aug 2014 · IEICE Electronics Express
  • Zong-Yi Chen · Chung-Chih Hung
    [Show abstract] [Hide abstract]
    ABSTRACT: In this paper, the DLL-based pulse-width modulation (PWM) digital-to-analog converter (DAC) is proposed to convert the output of multi-bit quantizer to a single-bit pulse-width modulated signal in the modified continuous-time sigma-delta modulators (CT-SDMs) with improved signal transfer function (STF). The DLL-based PWM DAC is more robust to clock jitter and excess loop delay (ELD) effects than conventional multi-bit DAC and other PWM DAC with similar speed and power requirements of the integrators in CT-SDMs. Furthermore, the proposed PWM DAC is based on inherently linear single-bit DAC, so the dynamic-element matching (DEM) techniques, which increase the circuit complexity and power consumption to compensate the mismatch of unit elements in the multi-bit DAC, can be removed in CT-SDMs.
    No preview · Conference Paper · Aug 2014
  • Fang-Ting Chou · Chia-Min Chen · Chung-Chih Hung
    [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents a high-speed, low-glitch, and low-power design for a 10-bit binary-weighted current-steering digital-to-analog converter (DAC). Instead of using large input buffers to drive a lot of current switches and re-timing latches, the proposed design uses variable-delay buffers with a compact layout to compensate for the delay difference among different bits, and to reduce glitch energy from 132 to 1.36 pV s during major code transitions. The measured spurious free dynamic range (SFDR) has been improved over 10 dB, as compared to DACs without variable-delay buffers. At 250 MS/s update rate, the proposed DAC achieves 56 dB SFDR for 0.67 MHz output frequency and 49 dB SFDR for 94 MHz output frequency with 50 Ω termination. For static performance, the measured integral nonlinearity (INL) and differential nonlinearity (DNL) is less than 1.6 and 1.8 LSB, respectively. The proposed DAC can be used in various applications in industry, including digital video, digital TV, wireless communication system, etc. This chip was implemented in TSMC 1P6M 0.18 μm CMOS technology and dissipates 19 mW from a single 1.8 V power supply.
    No preview · Article · May 2014 · Analog Integrated Circuits and Signal Processing
  • Source
    Zhe-Yang Huang · Chun-Chieh Chen · Chung-Chih Hung

    Preview · Article · Jan 2014
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents an inductorless dual-output switched-capacitor DC-DC converter employing pseudo-three-phase swap-and-cross control (PTPSCC) and an amplitude modulation mechanism (AMM). The AMM circuit scales the amplitudes of the driving signals for the switches according to the loading conditions in order to minimize switching losses. To reduce output ripples, average charge distribution, and improve regulation, the PTPSCC circuit continuously switches power transistors to deliver enough charge to the outputs by keeping at least one flying capacitor connected to each output. The two outputs were regulated at 2.5 V and 0.8 V with input ranges of 1.7-2 V. The maximum output loading was 100 mA for both outputs. A power efficiency of 90.5% was achieved at a maximum total output power of 330 mW with a switching frequency of 500 kHz. The maximal peak-to-peak output ripple voltages for the two outputs under 100 mA load currents were suppressed to below 26 mV and 20 mV, respectively.
    No preview · Conference Paper · Nov 2013
  • Chia-Min Chen · Tung-Wei Tsai · Chung-Chih Hung
    [Show abstract] [Hide abstract]
    ABSTRACT: This brief presents a low-dropout (LDO) voltage regulator without output capacitors that achieves fast transient responses by hybrid dynamic biasing. The hybrid dynamic biasing in the proposed transient improvement circuit is activated through capacitive coupling. The proposed circuit senses the LDO regulator output change so as to increase the bias current instantly. The proposed circuit was applied to an LDO regulator without output capacitors implemented in standard 0.35- μm CMOS technology. The device consumes only 25 μA of quiescent current with a dropout voltage of 180 mV. The proposed circuit reduces the output voltage spike of the LDO regulator to 80 mV when the output current is changed from 0 to 100 mA. The output voltage spike is reduced to 20 mV when the supply voltage varies between 1.3 and 2.3 V with a load current of 100 mA.
    No preview · Article · Sep 2013 · IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • Jun-Ren Su · Te-Wen Liao · Chung-Chih Hung
    [Show abstract] [Hide abstract]
    ABSTRACT: This paper proposes an all-digital fast-locking pulsewidth-control circuit with programmable duty cycle. In comparison with prior state-of-the-art methods, our use of two delay lines and a time-to-digital detector allows the pulsewidth-control circuit to operate over a wide frequency range with fewer delay cells, while maintaining the same level of accuracy. This paper presents a new duty-cycle setting circuit that calculates the desired output duty cycle without the need for a look-up table. The circuit was fabricated under the two-stage matrix converter 0.18-CMOS process. Results show that the proposed circuit performs well for an input operating frequency ranging from 200 to 600 MHz, and an input duty cycle ranging from 30% to 70%. It achieves a programmable output duty cycle ranging from 31.25% to 68.75% in increments of 6.25%.
    No preview · Article · Jun 2013 · IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • Chia-Min Chen · Chung-Chih Hung
    [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents a novel frequency compensation technique for a low-dropout (LDO) voltage regulator. Enhanced active feedback frequency compensation is employed to improve the frequency response. The proposed LDO is capable of providing high stability for current loads up to 150 mA with or without loading capacitors. The proposed LDO voltage regulator provides a loop bandwidth of 7.8 MHz under light loads and 6.5 MHz under heavy loads. The maximum undershoot and overshoot are 59 and 90 mV, respectively, for changes in load current within a 200-ns edge time, while the compensation capacitors only require a total value of 7 pF. This enables easy integration of the compensation capacitors within the LDO chip. The proposed LDO regulator was designed using TSMC 0.35-μm CMOS technology. With an active area of 0.14 mm2 (including feedback resistors), the quiescent current is only 40 μA. The input voltage ranges from 1.73 to 5 V for a loading current of 150 mA and an output voltage of 1.5 V. The main advantage of this approach is the stability of the LDO circuit when external load capacitors are connected, or even without load capacitors.
    No preview · Article · Apr 2013 · Analog Integrated Circuits and Signal Processing
  • Te-Wen Liao · Jun-Ren Su · Chung-Chih Hung
    [Show abstract] [Hide abstract]
    ABSTRACT: This brief presents a low-spur phase-locked loop (PLL) system for wireless applications. The low-spur frequency synthesizer randomizes the periodic ripples on the control voltage of the voltage-controlled oscillator to reduce the reference spur at the output of the PLL. A novel random clock generator is presented to perform the random selection of the phase frequency detector control for the charge pump in locked state. The proposed frequency synthesizer was fabricated in a TSMC 0.18-μm CMOS process. The proposed PLL achieved phase noise of -93 dBc/Hz with a 600-kHz offset frequency and reference spurs below -72 dBc.
    No preview · Article · Mar 2013 · IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • Chia-Min Chen · Kai-Hsiu Hsu · Chung-Chih Hung
    [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents a freewheel-charge-pump-controlled design for a single-inductor multiple-output (SIMO) DC–DC Converter. By applying the freewheel-charge-pump-controlled (FCPC) technique, the freewheel switching time is reused, and two extra charge-pump outputs are provided by time recycling, with no cost in time sequences. The converter has two step-up outputs and two charge-pump outputs that can be higher or lower than the input supply. The converter utilizes a 1 μH inductor, 4.7 μF charge-pump capacitors and 33 μF output capacitors at a frequency of 1 MHz. The proposed converter shows low cross-regulation and achieves a maximum loading current of 70 mA. Fabricated in a 0.18-μm CMOS process, the proposed circuit occupies 1.3 × 1.3 mm2. Experimental results demonstrate that the converter successfully generates four well-regulated outputs with a single inductor. The supply voltage ranged from 1.6 to 2.5 V and the load regulation performance was 0.08, 0.05, 1.7, and 1.9 mV/mA for VO1, VO2, VO3 and VO4, respectively.
    No preview · Article · Jan 2013 · Analog Integrated Circuits and Signal Processing
  • Te-Wen Liao · Jun-Ren Su · Chung-Chih Hung
    [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents a low phase-noise phase locked loop (PLL) system with a Multi-Phase Over-Sampling Charge Pump (MPOSCP) for wireless applications. The low phase-noise frequency synthesizer reduces ripples and noise on the control voltage of the ring voltage-controlled oscillator (VCO) as a means to control in-band noise at the output of the PLL. An MPOSCP is proposed to perform multi-phase over-sampling control for the charge pump (CP) in locked state. The proposed frequency synthesizer was fabricated using the TSMC 90-nm CMOS process. The prototype occupies 0.046mm2 active area, the reference frequency is 27 MHz, and the output frequency is 432 MHz with the total power consumption of 7 mW. The PLL achieved phase noise below -100 dBc/Hz from 15 Hz to 100 kHz with the reference spurs below-48 dBc.
    No preview · Conference Paper · Jan 2013
  • Te-Wen Liao · Jun-Ren Su · Chung-Chih Hung
    [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents a frequency synthesizer system with random pulsewidth matching technique and a sub-sampling charge pump. Through the randomization and average of the pulsewidth and the reduction of current mismatch, the frequency synthesizer can reduce the ripples on the control voltage of the voltage-controlled oscillator in order to reduce the reference spur at the output of the phase-locked loop. A random clock generator is used to perform a random selection control. To demonstrate the effectiveness of the proposed spur-reduction techniques, a 2.5 GHz to 2.7 GHz FLPLL was designed and fabricated using a TSMC 90-nm CMOS process. The proposed circuit can achieve a phase noise of -114 dBc/Hz at an offset frequency of 1 MHz and reference spurs below -74 dBc.
    No preview · Conference Paper · Jan 2013
  • Te-Wen Liao · Chia-Min Chen · Jun-Ren Su · Chung-Chih Hung
    [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents a fast locking phase-locked loop (FLPLL) system with reference-spur reduction techniques exploiting random pulsewidth matching and a sub-sampling charge pump. Through the randomization and average of the pulsewidth and the reduction of current mismatch, the frequency synthesizer can reduce the ripples on the control voltage of the voltage-controlled oscillator in order to reduce the reference spur at the output of the phase-locked loop. A random clock generator is used to perform a random selection control. The loop bandwidth of the system can be adjusted by the control voltage so as to reduce the locking time. To demonstrate the effectiveness of the proposed spur-reduction techniques, a 2.5 GHz to 2.7 GHz FLPLL was designed and fabricated using a TSMC 90-nm CMOS process. The proposed circuit can achieve a phase noise of -114 dBc/Hz at an offset frequency of 1 MHz and reference spurs below -74 dBc.
    No preview · Article · Dec 2012 · Circuits and Systems I: Regular Papers, IEEE Transactions on
  • Chia-Min Chen · Te-Wen Liao · Kai-Hsiu Hsu · Chung-Chih Hung
    [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents a freewheel-charge-pump-controlled design for a single-inductor multiple-output (SIMO) DC-DC Converter. By applying the freewheel-charge-pump-controlled (FCPC) technique, the freewheel switching time is reused, and two extra charge-pump outputs are provided by time recycling, with no cost in time sequences. The converter has two step-up outputs and two charge-pump outputs that can be higher or lower than the input supply. The proposed converter shows low cross-regulation and achieves a maximum loading current of 70 mA. Fabricated in a 0.18-μm CMOS process, the proposed circuit occupies only 1.3×1.3 mm2. Experimental results demonstrate that the converter successfully generates four wellregulated outputs with a single inductor. The supply voltage ranged from 1.6 V to 2.5 V and the load regulation performance was 0.08 mV/mA, 0.05mV/mA, 1.7 mV/mA, and 1.9 mV/mA for VO1, VO2, VO3 and VO4, respectively.
    No preview · Conference Paper · Sep 2012

Publication Stats

338 Citations
30.32 Total Impact Points

Institutions

  • 2005-2015
    • National Chiao Tung University
      • • Department of Electrical and Computer Engineering
      • • Department of Electronics Engineering
      • • Institute of Communications Engineering
      Hsin-chu-hsien, Taiwan, Taiwan
  • 2011
    • The Ohio State University
      Columbus, Ohio, United States
  • 2010
    • Industrial Technology Research Institute
      • Information and Communications Research Laboratories (ICL)
      Hsin-chu-hsien, Taiwan, Taiwan