Edoardo Bonizzoni

University of Pavia, Ticinum, Lombardy, Italy

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Publications (94)21.72 Total impact

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    ABSTRACT: This paper presents a voltage reference generator architecture and two different realizations of it that have been fabricated within a standard 0.18 μm CMOS technology. The architecture takes the advantage of utilizing a sampled-data amplifier (SDA) to optimize the power consumption. The circuits achieve output voltages on the order of 190 mV with temperature coefficients of 43 ppm/°C and 52.5 ppm/°C over the temperature range of 0 to 120°C without any trimming with a 0.8 V single supply. The power consumptions of the circuits are less then 500 nW while occupying an area of 0.2 mm2 and 0.08 mm2, respectively.
    No preview · Article · Nov 2015 · Microelectronics Journal
  • D.G. Muratore · E. Bonizzoni · F. Maloberti
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    ABSTRACT: A feasibility study of an 8-bit fast converter is presented. The advantages and limits of conventional SAR architectures are discussed and, on the basis of that, a possible optimal architecture is proposed. It uses a 4+4-bit scheme with combination of the DAC outputs in the current domain at the input of the latch. The circuit has been implemented with a 28 nm FDSOI CMOS technology. Post layout simulation results show 8bit of resolution at 1.2 GS/s.
    No preview · Article · Jul 2015
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    Hadi Heidari · Edoardo Bonizzoni · Umberto Gatti · Franco Maloberti
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    ABSTRACT: A Hall magnetic sensor working in the current domain and its electronic interface are presented. The paper describes the physical sensor design and implementation in a standard CMOS technology, the transistor level design of its high sensitive front-end together with the sensor experimental characterization. The current-mode Hall sensor and the analog readout circuit have been fabricated using a 0.18- CMOS technology. The sensor uses the current spinning technique to compensate for the offset and provides a differential current as an output signal. The measured sensor power consumption and residual offset are 120 and 50 , respectively.
    Full-text · Article · May 2015 · Circuits and Systems I: Regular Papers, IEEE Transactions on
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    ABSTRACT: Interference is a major concern in surface acoustic wave-less receiver architectures. This paper presents an architectural solution to design a quadrature band-pass Sigma Delta modulator in presence of interference signals. These interferences are rejected by using the built-in signal transfer function (STF) filtering action inside the quadrature modulator. The implementation of the STF filtering is achieved by means of feed-forward paths and does not require any additional active blocks. Simulations at the behavioral level on different design examples verify the architecture implementation and the effectiveness of the approach.
    No preview · Article · Apr 2015 · Analog Integrated Circuits and Signal Processing
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    ABSTRACT: Interference is a major concern in surface acoustic wave-less receiver architectures. This paper presents an architectural solution to design a quadrature band-pass \(\varSigma \varDelta \) modulator in presence of interference signals. These interferences are rejected by using the built-in signal transfer function (STF) filtering action inside the quadrature modulator. The implementation of the STF filtering is achieved by means of feed-forward paths and does not require any additional active blocks. Simulations at the behavioral level on different design examples verify the architecture implementation and the effectiveness of the approach.
    No preview · Article · Apr 2015 · Analog Integrated Circuits and Signal Processing
  • Yao Liu · Edoardo Bonizzoni · Alessandro D’Amato · Franco Maloberti
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    ABSTRACT: [email protected] /* */ paper describes a second-order 3-bit incremental converter, which employs a novel Smart-DEM algorithm to compensate for the mismatch among unity elements of the multi-level digital-to-analog converter. The design, which is fabricated in a mixed 0.18–0.5 μm CMOS technology, achieves 16.7-bit resolution over a 5-kHz bandwidth by using 256 clock periods per sample. A single-step chopping technique leads to a residual offset of 9.7 μV. The measured power consumption is 280 μW and the achieved figure of merit is 174.95 dB.
    No preview · Article · Mar 2015 · Analog Integrated Circuits and Signal Processing
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    Hadi Heidari · Edoardo Bonizzoni · Umberto Gatti · Franco Maloberti
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    ABSTRACT: This paper describes a magnetic Hall sensor working in current mode and its electronic interface. The microsystem uses the current spinning technique to compensate for the offset and provides a differential output signal current. The use of a low-noise chopper stabilized operational amplifier enables the integration of the signal current and ensures, after the sensor interface, a voltage sensitivity of 1660 V/A/mT (@ 25 kS/s) with a sensor bias current as low as 12 μA. The current-mode Hall sensor and the analog integrator read-out circuit have been fabricated with a 6-metal 0.18-μm standard CMOS technology. The current spinning technique reduces the offset to less than 50 μT (measured over 10 samples).
    Full-text · Conference Paper · Nov 2014
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    ABSTRACT: This paper presents a low power bandgap reference generator with 193-mV output voltage. The nominal supply voltage is 0.8 V, but the circuit can work with a supply down to 0.65 V. The circuit has been fabricated with a standard 0.18 μm CMOS technology and achieves a temperature coeflient of 43 ppm/°C for temperatures ranging from 0 to 120°C. A sampled-data amplifier consuming 140 nA and a reversed current-mode bandgap scheme draining 350 nA enable the achieved performance.
    No preview · Conference Paper · Sep 2014
  • Da Feng · Sai-Weng Sin · Edoardo Bonizzoni · Franco Maloberti
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    ABSTRACT: A four-path time interleaved current steering DAC is presented. It requires the same number of unity current generators of the plain counterpart, thanks to the use of a digital ΣΔ modulator, thus leading to a lower number of unity current switchings. The benefit is that the non-linearity caused by clock feedthrough is attenuated. Behavioral level simulation results show that the SFDR of a 12-bit DAC operating at 12 GS/s can be 60 dB.
    No preview · Conference Paper · Jun 2014
  • Yao Liu · Edoardo Bonizzoni · Franco Maloberti
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    ABSTRACT: This paper describes a multi-bit third-order incremental analog-to-digital (ADC) architecture and design considerations to achieve 18-bit resolution. The architecture uses multi-bit quantization in order to increase resolution and reduce the output swing of op-amps. The non-linearity due to the mismatch of unity elements of multi-bit DAC is properly compensated for with Smart-DEM algorithm. This 2+1 incremental architecture achieves 18-bit resolution with a 3-bit quantizer. Simulation results verify the target resolution achieved with 61 clock periods despite a large unity element mismatch (3σ = 0.5%).
    No preview · Conference Paper · Jun 2014
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    Hadi Heidari · Edoardo Bonizzoni · Umberto Gatti · Franco Maloberti
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    ABSTRACT: A magnetic Hall sensor working in the current-mode is presented. The proposed sensing device is composed by two Hall plates able to provide a differential current at the output nodes. The sensor, fabricated in a standard 0.18-μm CMOS technology, uses the spinning-current technique to compensate for the offset and obtains a sensitivity IHall/(B⊥Ibias) better than 0.02 T-1 for magnetic fields ranging from 0 to 10 mT.
    Full-text · Conference Paper · Jun 2014
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    ABSTRACT: This paper proposes the use of sampled-data operation in op-amps. The technique favors very low supply voltage and micro-power. After discussing the method at a general level, a possible sampled-data scheme is analyzed. Simulations with a low threshold technology show that a 0.5-V supply is possible. A version of the circuit, which has been integrated by using a standard 0.18-μm CMOS technology (with high thresholds), is able to operate at 0.65-V supply voltage. Simulation results show 42.5 dB of DC gain and 2.5-kHz bandwidth with 0.5-pF load capacitor. The power consumption is 63 nW. A pseudo-differential scheme doubles the consumed power and increases the DC gain by 6 dB.
    No preview · Conference Paper · Jun 2014
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    Hadi Heidari · Edoardo Bonizzoni · Umberto Gatti · Franco Maloberti
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    ABSTRACT: This paper presents a four-folded current-mode vertical Hall device. The current spinning technique is applied to a vertical Hall sensor driven in current mode to eliminate the offset and to increase the sensitivity. Different geometries have been studied and simulated by using a simulator based on finite element method. A four-folded three contacts vertical Hall device model displayed the lowest residual offset and the best sensitivity. Simulations results, obtained in two different environments, are compared and discussed. COMSOL results are validated with respect to the electrical behavior of an 8-resistor Verilog-A model implemented in Cadence environment. Simulations show that the achieved sensitivity can be better than 160 mT-1, a remarkable performance for vertical Hall sensors.
    Full-text · Conference Paper · Jun 2014
  • Yao Liu · Edoardo Bonizzoni · Alessandro D'Amato · Franco Maloberti
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    ABSTRACT: This paper presents a second-order 3-bit incremental converter, which uses a novel Smart-DEM algorithm for mismatch compensation of multi-level DAC unity elements. The circuit, fabricated in a mixed 0.18-0.5-μm CMOS technology, achieves more than 17-bit resolution over a 5-kHz bandwidth using 256 clock periods. A single-step chopping of the input stage leads to a residual offset of 9.7 μV. The measured SFDR and power consumption are -90 dB and 280 μW, respectively. The achieved Figure of Merit is 177.5 dB.
    No preview · Conference Paper · Sep 2013
  • Yao Liu · Edoardo Bonizzoni · Franco Maloberti
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    ABSTRACT: This paper describes the design method for highorder multi-bit incremental converters aiming at high resolution (> 14 bits) with Smart-DEM algorithm. Traditional 2nd and 3rd-order incremental ADCs use 1-bit quantizer. These structures lead to long conversion time for each sample to achieve the expected resolution and high power consumption due to the large output swing of the op-amps. Also, the fractional coefficients along the accumulation path that avoid instability degrade the performance. On the contrary, modulators employing multi-bit quantizer and DAC do not suffer from these problems. Although the mismatch of unity elements in the DAC causes non-linearity issue, this can be suppressed by Smart-DEM algorithm. Because the Smart-DEM algorithm is quite compact and easy to implement, the modulator benefits extra bits performance directly from the multi-bit DAC with affordable digital circuits overhead. In this paper several structures for incremental ADCs utilizing multi-bit quantizer are presented. The positive-and-negative DAC and the Smart-DEM algorithm are explained. With 3-bit quantizer, the simulation results show that the 2nd-order incremental ADC obtains 18-bit resolution with 256 clock periods.
    No preview · Conference Paper · May 2013
  • O. Belotti · E. Bonizzoni · F. Maloberti
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    ABSTRACT: This paper presents the design of a third-order ΣΔ modulator targeted for WCDMA applications. The architecture uses two operational amplifiers and distributed fully digital feed-forward paths to minimize the output swing of op-amps. Simulation results show that first and second integrator output swings are reduced by 88% and 75%, respectively. Post-layout simulation results of the modulator, designed in 65-nm CMOS technology, give a SNDR of 83 dB over a signal bandwidth of 2.2 MHz. The power consumption is 2.3 mW and the achieved FoM is equal to 172.8 dB.
    No preview · Conference Paper · Jan 2013
  • Y.B.N. Kumar · H. Caracciolo · E. Bonizzoni · A. Parra · F. Maloberti
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    ABSTRACT: This paper presents design and experimental results of a second-order, discrete-time, quadrature band-pass ΣΔ modulator targeted for wireless body area networks. The non-conventional architecture locks the intermediate frequency (IF) to the sampling frequency. Measurement results collected from a CMOS 0.18-μm prototype achieves a peak SNR of 55 dB over 100-kHz bandwidth and 40-dB SNR over 2.6-MHz bandwidth for a sampling frequency of 20 MHz with 1.96 mW power dissipation.
    No preview · Conference Paper · Jan 2013
  • N.Y.B. Kumar · Edoardo Bonizzoni · Amit Patra · Franco Maloberti
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    ABSTRACT: This paper presents a two-path design of quadrature band-pass ΣΔ modulators and discusses the architectural level implementation issues for power reduction. The methodology uses an architecture which locks IF frequencies to the sampling frequency. The basic delay based solution is converted into integrator based solution for the implementation. Robustness of the structure against the mismatch is analyzed and a two-path quadrature cascaded modulator is proposed to alleviate signal band gain error tone. Simulations at the behavioral level verify the architecture implementation and the effectiveness of the approach.
    No preview · Conference Paper · Jan 2013
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    H. Heidari · U. Gatti · E. Bonizzoni · F. Maloberti
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    ABSTRACT: The performances of a current-mode Hall sensor featuring output current signals are discussed. The current-mode approach is analyzed by applying for first time to our best knowledge the spinning current technique to Hall plate working in current-mode to eliminate offset and 1/f noise. Among different geometries that have been studied and simulated using COMSOL MultiphysicsTM, cross-shaped model displayed the lowest noise and residual offset and the best sensitivity. The COMSOL results determined a behavioral model implemented in Verilog-A for simulations in the Cadence environment. Simulations results achieved in COMSOL and in Cadence environment show the potentiality, thus demonstrating the effectiveness of the approach, for a possible use of the device with remarkable performances.
    Full-text · Conference Paper · Jan 2013
  • Oscar Belotti · Edoardo Bonizzoni · Franco Maloberti
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    ABSTRACT: A technique for the exact design of the noise transfer function of Continuous-Time (CT) Sigma-Delta modulators with arbitrary and multiple DAC responses and real op-amps is here presented. The approach, that presupposes linear behavior of active blocks, produces a CT modulator with the same noise shaping as its Discrete-Time counterpart. The method operates entirely in the time domain and accounts for non-idealities of real implementations such as finite gain and bandwidth of integrators. The procedure can be effectively implemented with circuit simulators to allow the exact design with transistor level blocks. A design example on a third-order scheme confirms the effectiveness of the method.
    No preview · Article · Oct 2012 · Analog Integrated Circuits and Signal Processing