[Show abstract][Hide abstract] ABSTRACT: This paper reports the development of an eco-friendly, low-cost and clean wet cleaning process in forming copper interconnections, especially on a copper surface at the bottom of the via. From analysis and electrical data, the components of post-etch residues are mainly formed by copper fluorides, copper oxides and silicon oxides. Therefore, diluted inorganic acid solutions are used to remove these polymers and a diluted amine solution is used to stabilize the copper surface after cleaning. These chemicals are treated by an effluent treatment facility, and are very cheap and clean. In the results of post-cleaning, the analysis data shows that the residues are removed, and the electrical data such as via chain yield, electro migration, etc., shows good performance.
[Show abstract][Hide abstract] ABSTRACT: Self-formed barrier technology using copper (Cu) manganese (Mn) alloy seed was applied for Cu dual-damascene interconnect with porous-SiOC/porous-PAr (k=2.3) hybrid dielectric for the first time. More than 90% yield for wiring and via-chain was obtained. 70% reduction in via resistance was confirmed compared with the conventional process. To estimate the moisture resistance property of self-formed barrier, via resistance change was measured with dummy density pattern. As the result, it was found that the resistance change ratio of via for self-formed barrier does not depend on the dummy density, probably due to the high moisture resistance property of self-formed oxide barrier. In addition, outgas at high temperature is found to be essential to form self-formed barrier for porous dielectric.
[Show abstract][Hide abstract] ABSTRACT: In order to realize the effective dielectric constant (k eff)=2.4 for 32 nm-node copper (Cu) dual-damascene (DD) interconnects, a spin-on-dielectric (SOD) SiOC (k=2.0) as the inter-level dielectric and plasma-induced damage restoration treatment were successfully demonstrated. It was obtained that good via resistance and stress-induced voiding (SiV) reliability. In addition, CoW-cap and thin SiC (k=3.5) and dual hard mask process using a metal layer was proposed to reduce the capacitance of dielectric diffusion barrier and protection layers in hybrid (PAr/SiOC) inter-layer dielectric (ILD) structure. As for the metallization, a self-formed MnSi<sub>x</sub>O<sub>y</sub> barrier technology was applied in hybrid ILD structure. Drastic reduction of via resistance and excellent electromigration and SiV performance were obtained for the first time in hybrid ILD structure