[Show abstract][Hide abstract] ABSTRACT: We have fabricated silicon nanowire N-MOSFETs using erbium disilicide (ErSi<sub>2-x</sub>) in a Schottky source/drain back-gated architecture. Although the subthreshold swing (~180 mV/dec) and drain-induced barrier lowering (~500 mV/V) are high due thick BOX as gate oxide, the fabricated Schottky transistors show acceptable drive current ~900 muA/mum and high I<sub>on</sub>/I<sub>off</sub> ratio (~10<sup>5</sup>). This is attributed to the improved carrier injection as a result of low Schottky barrier height (Phi<sub>b</sub>) of ErSi<sub>2-x</sub>/n - Si(~0.3 eV) and the nanometer-sized (~8 nm) Schottky junction. The carrier transport is found to be dominated by the metal-semiconductor interface instead of the channel body speculated from the channel length independent behavior of the devices. Furthermore, the transistors exhibit ambipolar characteristics, which are modeled using thermionic/thermionic-field emission for positive and thermionic-field emission for negative gate biases.
Full-text · Article · Nov 2008 · IEEE Electron Device Letters
[Show abstract][Hide abstract] ABSTRACT: A top-down approach of forming SiGe-nanowire (SGNW) MOSFET, with Ge concentration modulated along the source/drain (Si<sub>0.7</sub>Ge<sub>0.3</sub>) to channel (Si<sub>0.3</sub>Ge<sub>0.7</sub>) regions, is presented. Fabricated by utilizing a pattern-size-dependent Ge-condensation technique, the SGNW heterostructure PMOS device exhibits 4.5times enhancement in the drive current and transconductance (G<sub>m</sub>) as compared to the homojunction planar device (Si<sub>0.7</sub>Ge<sub>0.3</sub>). This large enhancement can be attributed to several factors including Omega-gated nanowire structure, enhanced hole injection efficiency (due to valence band offset), and improved hole mobility (due to compressive strain and Ge enrichment in the nanowire channel).
[Show abstract][Hide abstract] ABSTRACT: Fabrication of germanium-on-insulator (GeOI) substrates with a 160-nm-thick Ge layer is reported. Such thick GeOI substrates
were fabricated by thermal intermixing and subsequent condensation of epitaxially grown high-Ge- content SiGe on Si-on-insulator
(SOI) substrates. Transmission electron microscopy revealed that the GeOI layer was single crystalline. The high-resolution
rocking curve and reciprocal lattice map obtained from X-ray diffraction measurements showed a relaxed GeOI. This was further
confirmed by micro-Raman measurements, where the Ge-Ge optical phonon peak shift represented a nearly strain-free Ge layer.
Using this methodology, GeOI substrates with Ge layers 120–160nm thick have been fabricated with thickness variations of
less than 4nm across 200mm wafers.
Full-text · Article · Jun 2008 · Journal of Electronic Materials
[Show abstract][Hide abstract] ABSTRACT: In this paper, we report the first demonstration of n-channel FinFETs with in-situ doped silicon-carbon (Si<sub>1-y</sub>C<sub>y</sub> or SiC:P) source and drain (S/D) stressors. New key features incorporated in this work for performance enhancement includes record-high substitutional carbon concentration C<sub>sub</sub> of 2.1%, high in-situ phosphorus doping concentration in S/D, extended Pi -shaped S/D stressors that wrap around the Si fin for maximum lattice interaction, lateral stressor encroachment under the spacer for closer promixity to channel region for maximum channel stress as well as reduced S/D extension resistances.
[Show abstract][Hide abstract] ABSTRACT: We report the integration of a new liner stressor comprising diamond-like carbon (DLC) film over a p-channel transistor. A high compressive stress of 6.5 GPa was achieved in a high-stress film with a thickness of 27 nm. A 74% enhancement in drive current was observed for the strained device with DLC liner as compared to a control device without DLC liner. Due to its much higher intrinsic stress value compared to conventional SiN films, a thinner DLC layer can induce comparable amount of stress in the transistor channel compared to a thicker SiN. The DLC material is a potential next-generation high-stress and low-permittivity liner stressor material suitable for application in transistors with aggressively scaled pitch dimensions.
No preview · Article · Mar 2008 · IEEE Electron Device Letters
[Show abstract][Hide abstract] ABSTRACT: To explore the potential of nickel-silicide:carbon (NiSi:C) as contact technology for MOSFETs with silicon-carbon (Si:C) source/drain (S/D) regions, we examined the effects of incorporating 1.0 at.% of carbon in Si prior to nickel silicidation. The addition of carbon was found to improve the morphological and phase stability of NiSi:C contacts. This is possibly due to the presence of carbon at the NiSi:C grain boundaries and NiSi:C/Si interface, which will modify the grain-boundary and interfacial energies. This will influence the kinetics of NiSi:C silicidation. In this letter, we have also demonstrated the first integration of NiSi:C contacts in MOSFETs with Si:C S/D regions. We further show that NiSi:C silicidation suppresses the formation of active deep-level defects, leading to superior n<sup>+</sup>/p junction characteristics.
No preview · Article · Feb 2008 · IEEE Electron Device Letters
[Show abstract][Hide abstract] ABSTRACT: We report a new silicon-germanium-tin (SiGeSn) source and drain stressor with large lattice-mismatch with respect to Si or SiGe for channel strain engineering, and its integration in a SiGe-channel p-FET for performance enhancement. A novel CMOS-compatible process was developed to incorporate Sn in SiGe S/D with high levels of Sn-substitutionality: Sn implant into Si<sub>0.75</sub>Ge<sub>0.25</sub> source and drain (S/D) regions, followed by either excimer laser annealing (LA) or solid phase epitaxy (SPE) to restore S/D crystallinity. Sub-50 nm p-FETs were fabricated. With a substitutional Sn concentration of 8% in SiGe S/D regions, equivalent to forming Si<sub>0.4</sub>Ge<sub>0.6</sub> in the S/D region, enhancement of I<sub>Dsat</sub> and hole mobility are 82% and 135%, respectively, over control p- FETs without Sn incorporation. With the first demonstration of SiGeSn S/D stressors, we provide a technology extension to SiGe S/D technology for further p-FFT enhancement.
[Show abstract][Hide abstract] ABSTRACT: We report a new liner stressor comprising a diamond-like carbon (DLC) layer with very high intrinsic stress for boosting the performance of p-channel transistors. A record-high intrinsic compressive stress of more than 6 GPa is demonstrated, well exceeding values currently achievable with the conventional SiN contact etch-stop layer (CESL). Two major advantages of the DLC layer are lower permittivity and significantly higher compressive stress, therefore enabling further pitch and density scaling with less performance compromise. We integrated the DLC liner stressor with nanoscale SOI p-FETs, demonstrating significant drive current I<sub>D,sat</sub> enhancement of up to 58% over control devices without liner stressor.
[Show abstract][Hide abstract] ABSTRACT: This letter reports on the noise degradation mechanism in SiGe- and SiGeC-surface channel p -type metal-oxide-semiconductor field-effect transistors (p MOSFETs ) . Compared to their Si reference, the surface SiGe p MOSFETs show only slightly lower or even comparable noise (at low gate bias), while the SiGeC devices exhibit higher noise amplitude for the full bias range, unlike previously reported buried SiGe p MOSFETs with significantly improved noise over their Si control. The degradation can be attributed to Si-cap consumption and thus the cancellation of buried channel operation. [C] incorporation further degrades noise characteristics due to inferior quality of epilayer and higher interface trap density.
Full-text · Article · Jan 2008 · Applied Physics Letters
[Show abstract][Hide abstract] ABSTRACT: We studied erbium germanosilicide films formed on relaxed p-type Si1-x Gex (100) (x=0-0.3) virtual substrates by conventional rapid thermal annealing (RTA) at temperatures of 500-700°C. Two dimensional X-ray diffraction and pole figure measurements revealed that the silicide films formed were epitaxial Er (Si1-x Gex) 2-y with orientation relationship Er (Si1-x Gex) 2-y (1 1- 00) -  ∥ Si1-x Gex (001)  or Er (Si1-x Gex) 2-y (1 1- 00)  ∥ Si1-x Gex (001) [1- 10]. Schottky barrier height, φBp, of the Er (Si1-x Gex) 2-y p- Si1-x Gex (100) contact was found to decrease from 0.79 to 0.62 eV with increasing Ge (from 0 to 30%), implying a slight increase in its barrier height for electrons, φBneff, from 0.33 to 0.37 eV.
No preview · Article · Jan 2008 · Journal of The Electrochemical Society
[Show abstract][Hide abstract] ABSTRACT: Further enhancement of performance in a strained p-channel multiple-gate or fin field-effect transistor (FinFET) device is demonstrated by utilizing an extended-Pi-shaped SiGe source/drain (S/D) stressor compared to that utilizing only Pi-shaped SiGe S/D. With the usage of a longer hydrofluoric acid cleaning time prior to the selective-epitaxy-raised S/D growth, a recess in the buried oxide is formed. This recess allows the subsequent SiGe growth on the fin sidewalls of the S/D regions to extend into the recessed buried oxide to provide a larger compressive stress in the channel for enhanced electrical performance compared to a device with SiGe S/D stressor. Process simulation shows that longitudinal compressive stress in the channel region is higher in a FinFET with extended-Pi-SiGe S/D than that with Pi-SiGe S/D. An enhancement of 26% in the drive current was experimentally observed, demonstrating further boost in enhancement of strained p-channel FinFET with little additional cost using this novel process.
No preview · Article · Nov 2007 · IEEE Electron Device Letters
[Show abstract][Hide abstract] ABSTRACT: By removing the SiN gate spacers in n-channel FinFETs with Silicon-Carbon (SiC) Source and Drain (S/D) stressors, the mechanical stress equilibrium is perturbed. Higher tensile channel stress can be achieved, after the transistor structure attains mechanical equilibrium once again after spacer removal. This stress increase results in up to ~15 % further I<sub>Dsat</sub> enhancement over strained SiC S/D FinFETs with spacers intact. Peak G<sub>m</sub> is enhanced by ~33 %.
[Show abstract][Hide abstract] ABSTRACT: In this work, the authors demonstrate a fabrication methodology for obtaining a thick (∼250 nm ) high Ge content SiGe-on-insulator (SGOI) film. About 800 nm thick low Ge content (∼25%) SGOI film was fabricated by intermixing SiGe and Si through thermal annealing of a superlattice comprising of 60 periods of Si <sub>0.7</sub> Ge <sub>0.3</sub> and Si on silicon-on-insulator (SOI) substrate. A combination of oxidation and annealing processes was used to condense and diffuse the Ge through SiGe film to obtain thick Si <sub>0.2</sub> Ge <sub>0.8</sub> OI . It is also found that the oxidation termination is due to residual stress in the thick SGOI layer. The transmission electron microscopy measurements showed that the Si <sub>0.2</sub> Ge <sub>0.8</sub> OI film exhibits a single crystalline nature with an orientation that is the same as the starting SOI. X-ray diffraction measurements confirmed that the in-plane strain of the SGOI layers is compressive or nearly relaxed.
Full-text · Article · Jun 2007 · Applied Physics Letters
[Show abstract][Hide abstract] ABSTRACT: The letter presents the fabrication processes to realize high Ge content SiGe on insulator using Ge condensation technique with and without intermittent oxide etching. During condensation process with intermittent silicon oxide etching, the formation of an undesirable amorphous SiGeO is observed. This is due to uncontrolled oxidation of silicon when the oxide layer is etched away. In the case of Ge condensation process without oxide etching, the authors could achieve a SiGe layer with 91% Ge concentration. A crystalline SiGeO layer at the interfaces of the top silicon oxide and buried oxide with SiGe was also observed. Possible formation mechanisms of amorphous and crystalline SiGeO are presented. Ge condensation process without SiO2 etching utilizes four steps of oxidation and intermittent annealing cycles at each temperature resulted in Si0.09Ge0.91OI substrate.
Full-text · Article · Jan 2007 · Applied Physics Letters
[Show abstract][Hide abstract] ABSTRACT: A novel method for realizing arrays of vertically stacked (e.g., times3 wires stacked) laterally spread out nanowires is presented for the first time using a fully Si-CMOS compatible process. The gate-all-around (GAA) MOSFET devices using these nanowire arrays show excellent performance in terms of near ideal sub-threshold slope (<70 mV/dec), high I<sub>on</sub>/I<sub>off</sub> ratio (~10<sup>7</sup>), and low leakage current. Vertical stacking economizes on silicon estate and improves the on-state I<sub>DSAT</sub> at the same time. Both n- and p-FET devices are demonstrated
[Show abstract][Hide abstract] ABSTRACT: Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K. SiNW width is controlled in 1 nm steps and varied from 3 to 6 nm. Devices show high drive current (2.4 mA/mum for n-FET, 1.3 mA/mum for p-FET), excellent gate control, and reduced sensitivity to temperature. Strong evidences of carrier confinement are noticed in term of I<sub>d</sub>-V<sub>g</sub> oscillations and shift in threshold voltage with SiNW diameter. Orientation impact has been investigated as well
[Show abstract][Hide abstract] ABSTRACT: A novel strained-SiGe n-channel field-effect transistor (nFET) featuring silicon-carbon (Si<sub>0.99</sub>C<sub>0.01</sub>) source/drain (S/D) stressors and tensile stress nitride (SiN) liner is demonstrated for the first time. The silicon-carbon Si<sub>1-y</sub>C <sub>y</sub>, material is pseudomorphically grown by selective epitaxy and the carbon mole fraction y incorporated is 1%. Si<sub>0.99</sub>C <sub>0.01</sub> S/D was employed to induce uniaxial tensile strain in the SiGe channel, leading to enhancement in electron mobility. Devices with gate length L<sub>G</sub> down to 50 nm were fabricated. Up to 55% higher saturation drive current I<sub>d,sat</sub> was achieved in the strained-SGOI nFETs over control devices. In addition, the incorporation of a tensile stress SiN liner improves I<sub>d,sat</sub> by an additional 15%
[Show abstract][Hide abstract] ABSTRACT: A two-step rapid thermal annealing (RTA) nickel salicidation process was employed to fabricate 0.1-mum gate length CMOS transistors. Excess salicidation, common in the conventional one-step RTA NiSi process, is effectively suppressed by this approach, which is confirmed by transmission electron microscopy (TEM) images. More improvements due to two-step NiSi are observed in NMOS than in PMOS transistors: The n<sup>+</sup>-p junction diode with two-step NiSi exhibits lower reverse leakage and higher breakdown voltage than the one-step silicided diode. For the first time, it is found that two-step NiSi NMOS exhibits significant reduction in off-state leakage (~5times) and low-frequency noise (up to two orders of magnitude) over one-step NiSi NMOS, although there is not much difference in PMOS transistors
No preview · Article · Nov 2006 · IEEE Electron Device Letters