[Show abstract][Hide abstract] ABSTRACT: The shallow trench isolation (STI) stress effect along the length direction on short-channel MOSFET devices has already been widely studied. However, the effect along the width direction has seldom been specifically analyzed. In this paper, we combine a novel charge-based capacitance measurement technique, which is used to extract the intrinsic of MOSFET devices, and the split capacitance-voltage method to extract the mobility of devices with various channel widths. Although it is already known that under the influence of compressive STI stress along the width direction the mobility of both NMOS and PMOS devices will degrade with decreasing width, it is the first time to quantify the impact of this STI stress component on MOSFET devices.
No preview · Article · Jul 2008 · IEEE Electron Device Letters
[Show abstract][Hide abstract] ABSTRACT: In this work, we describe a novel operation of charge-injection-induced error-free charge-based capacitance measurement (CIEF CBCM) method. This method has the simplest test structure among various CBCM methods by using only one N/PMOS pair. CIEF CBCM has the advantage of being free from charge-injection-induced errors and of efficient layout area usage. It is very suitable for industrial applications for large amounts of accurate capacitance characterizations with a limited layout area. Besides, CIEF CBCM is also implemented for investigating the impact of floating dummy metal fills on interconnect capacitance directly from silicon data.
No preview · Article · Mar 2006 · IEEE Transactions on Semiconductor Manufacturing