[Show abstract][Hide abstract] ABSTRACT: Reliability of power-electronic modules is of paramount importance for the commercial success of various types of electric vehicles. In this paper, we study the technical feasibility of detecting and utilizing early symptoms and warning signs of power-module degradation due to thermomechanical stress and fatigue and develop a prognostic system that can monitor the state of health of the power modules in electric, hybrid, and fuel-cell vehicles. A special degradation trace on the V<sub>CEsat</sub> of the insulated-gate bipolar-transistor modules was observed by a power-cycling accelerated test, which was not reported in literatures. A prognostic system based on utilizing the aforementioned trace is then developed. The system consists of the hardware architecture and current adaptive-algorithm-based software architecture. In addition, this prognostic system hardly increases the hardware cost on existing vehicle-driver system. An extensive simulation based on MATLAB/Simulink verifies the developed prognostic system.
[Show abstract][Hide abstract] ABSTRACT: A novel concept of on-chip bondwire inductors with ferrite epoxy coating is proposed to provide a cost effective approach realizing power systems on chip (SOC). A Q factor of 30-40 is experimentally demonstrated which represents an improvement by a factor of 3-30 over the state-of-the-art MEMS micromachined inductors. More importantly, the bondwire inductors can be easily integrated into power SOC manufacturing processes with minimal changes, and open enormous possibilities for realizing cost-effective, high current, high efficiency power SOC's.
[Show abstract][Hide abstract] ABSTRACT: This paper presents a comparative study of lateral and trench power MOSFETs in hard switching synchronous buck converters operating in the multi-MHz frequency range based on a mixed-mode device/circuit modeling approach. Detailed power loss analysis is performed for the control and synchronous MOSFETs. It is observed that the inherently low gate charge QG of lateral MOSFETs offers significant reduction in gate drive losses, which become increasingly important in the multi-MHz frequency range and especially light load conditions. Furthermore, the power loss due to the reverse recovery of the SyncFET body diode becomes a major limiting factor in the MHz frequency range for both trench and lateral MOSFETs. This factor will eventually determine the maximum practical switching frequency of the buck converter.
[Show abstract][Hide abstract] ABSTRACT: Realistic estimation of power MOSFET switching losses is critical for predicting the maximum junction temperature and efficiency of power electronics circuits. The purpose of this paper is to investigate the internal physics of MOSFET switching processes using a physically based semiconductor device modeling approach, and subsequently examine the commonly used power loss calculation method based on the new physical insights. The widely accepted output capacitance loss term in this calculation method is found to be redundant and erroneous. In addition, the current method of approximating switching times with power MOSFET gate charge parameters grossly overestimates the switching power loss. This paper recommends a new MOSFET gate charge parameter specification and an effective switching time estimation method to compensate for the power loss calculation error introduced by the two slope voltage transition waveform of the power MOSFET
[Show abstract][Hide abstract] ABSTRACT: DC/DC converters to power future CPU cores mandate low-voltage power metal-oxide semiconductor field-effect transistors (MOSFETs) with ultra low on-resistance and gate charge. Conventional vertical trench MOSFETs cannot meet the challenge. In this paper, we introduce an alternative device solution, the large-area lateral power MOSFET with a unique metal interconnect scheme and a chip-scale package. We have designed and fabricated a family of lateral power MOSFETs including a sub-10 V class power MOSFET with a record-low R<sub>DS(ON)</sub> of 1mΩ at a gate voltage of 6V, approximately 50% of the lowest R<sub>DS(ON)</sub> previously reported. The new device has a total gate charge Q<sub>g</sub> of 22nC at 4.5V and a performance figures of merit of less than 30mΩ-nC, a 3× improvement over the state of the art trench MOSFETs. This new MOSFET was used in a 100-W dc/dc converter as the synchronous rectifiers to achieve a 3.5-MHz pulse-width modulation switching frequency, 97%-99% efficiency, and a power density of 970W/in<sup>3</sup>. The new lateral MOSEFT technology offers a viable solution for the next-generation, multimegahertz, high-density dc/dc converters for future CPU cores and many other high-performance power management applications.
Preview · Article · Feb 2006 · IEEE Transactions on Power Electronics