Publications (2)0 Total impact
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ABSTRACT: A 2.5-Gb/s current-mode logic (CML) transceiver is implemented in 0.13 - mum CMOS technology for serial inter-chip interconnection. To compensate the channel attenuation and other impairments, pre-emphasis circuit is included at the transmitter and equalizer at the receiver. 6-GHz 3 dB bandwidth is achieved through the use of active inductors instead of online spiral inductors. DC offset compensate circuits are employed in the output and input buffers to keep the common mode voltage stable. Layout simulation demonstrates the effectiveness of the transceiver. This transceiver consumes only 160 mw of power with 2.5v power supply. The die area of transmitter and receiver are 0.015 mm<sup>2</sup>, 0.01 mm<sup>2</sup> respectively. The transceiver can be operated at 2.5-Gb/s with 100 mv receiver sensitivity.
Conference Paper: A design of high speed AGTL+ output buffer[Show abstract] [Hide abstract]
ABSTRACT: AGTL+ (assisted Gunning transceiver logic+) signal transmission and interface technology are analyzed in this paper. To resolve the problem on such short high-level duration time in traditional design, we have proposed an auxiliary charged circuit structure. According to what I have analyzed, we design and realize an AGTL+ interface circuit, which is completely compatible with Itanium 2 interface and has high-speed and high noise margin. The operating frequency of circuit reaches to 500MHz by SPICE simulation in the condition of 0.18μm standard CMOS process.
National University of Defense Technology
Ch’ang-sha-shih, Hunan, China
- Institute of Microelectronics and Microprocessors