Harald Gossner

Infineon Technologies, München, Bavaria, Germany

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Publications (111)92.45 Total impact

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    ABSTRACT: Shallow-trench isolation drain extended pMOS (STI-DePMOS) devices show a distinct two-stage breakdown. The impact of p-well and deep-n-well doping profile on breakdown characteristics is investigated based on TCAD simulations. Design guidelines for p-well and deep-n-well doping profile are developed to shift the onset of the first-stage breakdown to a higher drain voltage and to avoid vertical punch-through leading to early breakdown. An optimal ratio between the OFF-state breakdown voltage and the $ON$-state resistance could be obtained. Furthermore, the impact of p-well/deep-n-well doping profile on the figure of merits of analog and digital performance is studied. This paper aids in the design of STI drain extended MOSFET devices for widest safe operating area and optimal mixed-signal performance in advanced system-on-chip input-output process technologies.
    No preview · Article · Oct 2015 · IEEE Transactions on Electron Devices
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    ABSTRACT: In this paper, we study breakdown characteristics in shallow-trench isolation (STI)-type drain-extended MOSFETs (DeMOS) fabricated using a low-power 65-nm triple-well CMOS process with a thin gate oxide. Experimental data of p-type STI-DeMOS device showed distinct two-stage behavior in breakdown characteristics in both OFF- and ON-states, unlike the n-type device, causing a reduction in the breakdown voltage and safe operating area. The first-stage breakdown occurs due to punchthrough in the vertical structure formed by p-well, deep n-well, and p-substrate, whereas the second-stage breakdown occurs due to avalanche breakdown of lateral n-well/p-well junction. The breakdown characteristics are also compared with the STI-DeNMOS device structure. Using the experimental results and advanced TCAD simulations, a complete understanding of breakdown mechanisms is provided in this paper for STI-DeMOS devices in advanced CMOS processes.
    No preview · Article · Oct 2015 · IEEE Transactions on Electron Devices
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    ABSTRACT: In this paper, we report drain-extended MOS device design guidelines for the RF power amplifier (RF PA) applications. A complete RF PA circuit in a 28-nm CMOS technology node with the matching and biasing network is used as a test vehicle to validate the RF performance improvement by a systematic device design. A complete RF PA with 0.16-W/mm power density is reported experimentally. By simultaneous improvement of device-circuit performance, 45% improvement in the circuit RF power gain, 25% improvement in the power-added efficiency at 1-GHz frequency, and 5× improvement in the electrostatic discharge robustness are reported experimentally.
    No preview · Article · Oct 2015 · IEEE Transactions on Electron Devices
  • H. Gossner · C. Duvvury
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    ABSTRACT: System-level ESD robustness is a crucial feature for any electronic system. To achieve the required level of robustness at the lowest cost a design concept is applied which assures matching between PCB protection components and IC IO behaviour under system ESD discharge. It is now widely referred to as system efficient ESD design (SEED). A thorough characterization of the high current behaviour of IO circuit and on-board protection elements provides the necessary data for a simulation based co-design of on-chip and on-board protection measures. The constraints for characterization and modeling are discussed. Applying this methodology allows the development of a cost optimized system-level ESD protection throughout the stages of a system design. © 2015 Elsevier Ltd. All rights reserved.. All rights reserved.
    No preview · Article · Oct 2015 · Microelectronics Reliability
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    ABSTRACT: In this paper, for the first time, the key design parameters of a shallow trench isolation-based drain-extended MOS transistor are discussed for RF power applications in advanced CMOS technologies. The tradeoff between various dc and RF figures of merit (FoMs) is carefully studied using well-calibrated TCAD simulations. This detailed physical insight is used to optimize the dc and RF behavior, and our work also provides a design window for the improvement of dc as well as RF FoMs, without affecting the breakdown voltage. An improvement of 50% in $R_{mathrm{{scriptscriptstyle ON}}}$ and 45% in RF gain is achieved at 1 GHz. Large-signal time-domain analysis is done to explore the output power capability of the device.
    No preview · Article · Oct 2015 · IEEE Transactions on Electron Devices
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    ABSTRACT: This paper explores drain extended MOS (DeMOS) device design guidelines for an area scaled, ESD robust integrated radio frequency power amplifier (RF PA) for advanced system-on-chip applications in 28nm node CMOS. Simultaneous improvement of device-circuit performance and ESD robustness is discussed for the first time. By device design optimization a 45% increase in gain and 25% in power-added efficiency of RF PA at 1GHz, and 5× improvements in ESD robustness are reported experimentally.
    No preview · Article · Feb 2015 · Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International
  • M. Shrivastava · H. Gossner
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    ABSTRACT: ESD behavior of metallic carbon nanotubes (CNTs) is explored. Unique TLP I-V characteristics and failure mechanism of carbon shells are discussed. ESD failure in CNTs is attributed to shell burning. It was found that CNT interconnect changes resistance in steps of fundamental quantum resistance (hI2e2) after individual shell burning.
    No preview · Article · Nov 2014
  • Source
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    ABSTRACT: A comprehensive model of a clock line including large and small signal pin parameters, as well as channel parameters is presented. The small signal model allows analysis of in-band interference which can lead to soft failures, while large signal models allow for the simulation of current sharing between driver/receiver pin pairs.
    Full-text · Conference Paper · Jul 2014
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    ABSTRACT: A comprehensive study of electrostatic discharge (ESD) characterization of atomically thin graphene is reported. In a material comprising only a few atomic layers, the thermally destructive second breakdown transmission line pulsing (TLP) current (It2) reaches a remarkable 4 ${rm mA}/mu{rm m}$ for 100-ns TLP and ${sim}{rm 8}~{rm mA}/mu{rm m}$ for 10-ns TLP or an equivalent current density of ${sim}3times 10^{8}$ and $4.6times 10^{8}~{rm A}/{rm cm}^{2}$ , respectively. For ${sim}{rm 5}hbox{-}{rm nm}$ thick $({sim}{rm 15}~{rm layers})$ graphene film, It2 reaches 7.4 ${rm mA}/mu{rm m}$ for 100-ns pulse. The fact that failure occurs within the graphene and not at the contacts indicates that intrinsic breakdown properties of this new material can be appropriately characterized using short-pulse stressing. Moreover, unique gate biasing effects are observed that can be exploited for novel applications including robust ESD protection designs for advanced semiconductor products. This demonstration of graphene's outstanding robustness against high-current/ESD pulses also establishes its unique potential as transparent electrodes in a variety of applications.
    No preview · Article · Jun 2014 · IEEE Transactions on Electron Devices
  • Mayank Shrivastava · Neha Kulshrestha · Harald Gossner
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    ABSTRACT: Electrostatic discharge (ESD) investigations on the multiwalled carbon nanotubes (MWCNTs) are performed for the first time. A novel ESD failure mechanism of subsequent shell burning has been discovered. By using nanosecond pulse measurements, a new insight into metal-to-carbon nanotube (CNT) contact behavior could be achieved. Clear signature of two very different conduction mechanisms and related failure types at high current injection has been found. By determining the time to failure, an Arrhenius-like relation was extracted, which was explained by the oxidation of CNT shells. Finally, an extraordinary ESD failure current density of MWCNT of $hbox{1.2} times hbox{10}^{9} hbox{A/cm}^{2}$ could be shown.
    No preview · Article · Mar 2014 · IEEE Transactions on Device and Materials Reliability
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    ABSTRACT: This paper presents a device-circuit co-design approach to achieve a low swing, high speed 1.2-5 V level shifter (LS) using drain extended MOS (DeMOS) transistors for system on chip applications in advance CMOS technologies. Limiting factors of the high-voltage devices during transients are identified and accordingly it is shown that the maximum operating frequency of traditional LS can be increased by at least a factor of two. It is demonstrated that optimization of key device parameters of the DeMOS transistor enhances the maximum clock frequency to more than 1 GHz while preserving the device breakdown voltage and duty cycle of the level shifted signal.
    No preview · Article · Nov 2013 · IEEE Transactions on Electron Devices
  • Source
    P. Maheshwari · B. Orr · H. Gossner · D. Pommerenke · W. Stadler
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    ABSTRACT: A systematic method for evaluating soft fail robustness of a DUT subsystem is presented and demonstrated on a camera MIPI interface. Two different mobile phone platforms are studied under TLP injection while various methods for extracting failure thresholds and localization are applied. The root cause for the soft-failure threshold discrepancy is left for future work.
    Full-text · Conference Paper · Oct 2013
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    ABSTRACT: Advanced mobile applications demand low power and high performance systems. In this paper, a technology computer aided design (TCAD)-based feasibility investigation of a recently proposed area tunneling field effect transistor (FET) structure is carried out from the point of high volume and ultralow power mobile applications. We demonstrate that for realization of future ultralow power and high performance systems, unique properties of area tunneling class of tunnel FET structures need to be employed. These devices are realized by engineering the tunneling region profile and tunneling cross-sectional area. The optimized devices are found to leverage up to ~ 7× energy reduction when compared with the 20-nm node MOS device options while meeting the high performance targets. Device design insights for such an area tunneling class of tunnel FET structures are discussed in this paper for the first time. It is shown that by lowering the supply voltage below 0.5 V, up to 10× reduction of the energy delay product is feasible by using area tunneling devices.
    No preview · Article · Aug 2013 · IEEE Transactions on Electron Devices
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    ABSTRACT: The phenomenon of impact-ionization is proposed to be leveraged for a novel biosensor design scheme for highly efficient electrical detection of biological species. Apart from self-consistent numerical simulations, an analytical formalism is also presented to provide physical insight into the working mechanism and performance of the proposed sensor. It is shown that using the impact-ionization field-effect-transistor (IFET) based biosensor, it is possible to obtain an increase in sensitivity of around 4 orders of magnitude at low biomolecule concentration and around 6 orders of magnitude at high biomolecule concentration compared to that in conventional FET (CFET) biosensors. Moreover, IFET biosensors can lead to significant reduction (around 2 orders of magnitude) in response time compared to CFET biosensors.
    No preview · Article · May 2013 · Applied Physics Letters
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    ABSTRACT: A gas-sensor based on tunnel-field-effect-transistor (TFET) is proposed that leverages the unique current injection mechanism in the form of quantum-mechanical band-to-band tunneling to achieve substantially improved performance compared to conventional metal-oxide-semiconductor field-effect-transistors (MOSFETs) for detection of gas species under ambient conditions. While nonlocal phonon-assisted tunneling model is used for detailed device simulations, in order to provide better physical insights, analytical formula for sensitivity is derived for both metal as well as organic conducting polymer based sensing elements. Analytical derivations are also presented for capturing the effects of temperature on sensor performance. Combining the developed analytical and numerical models, intricate properties of the sensor such as gate bias dependence of sensitivity, relationship between the required work-function modulation and subthreshold swing, counter-intuitive increase in threshold voltage for MOSFETs and reduction in tunneling probability for TFETs with temperature are explained. It is shown that TFET gas-sensors can not only lead to more than 10 000× increase in sensitivity but also provide design flexibility and immunity against screening of work-function modulation through non-specific gases as well as ensure stable operation under temperature variations.
    No preview · Article · Jan 2013 · Applied Physics Letters
  • H. Gossner
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    ABSTRACT: While CMOS downscaling approaches its limits, ESD protection design is facing significant challenges. Technology measures which facilitate further technology scaling enhance the sensitivity of the devices against ESD stress. At the same time demanding performance requirements more and more limit the options of circuit solutions for ESD protection. In consequence ESD qualification goals for ICs had to be reviewed and adjusted. However, the need of ESD robust systems cannot be compromised. To balance and match IC level protection and PCB protection measures the concept of system efficient ESD design (SEED) has recently been introduced.
    No preview · Conference Paper · Jan 2013
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    ABSTRACT: form only given. Have you ever wondered how other companies organize their ESD design teams? Join us as we attempt to benchmark successful organization strategies as practiced by Workshop participant companies. We expect divergent opinions and a healthy debate on the advantages and disadvantages of the various approaches. Is your ESD design team embedded within an I/O design team, or independent? Are you in a central technology support organization, or in a product group? Does your company leverage outside ESD design contractors? Does your ESD design team organization drive your ESD support model? For example are ESD design solutions full custom for each I/O library, or offered as generic solutions in a process technology? Do you have separate engineers for ESD IP design and SoC support? How many IP sets or SoCs is each engineer expected to support? This Workshop should give you valuable insight into industry ESD team organization strategies to discuss with your work peers and managers.
    No preview · Conference Paper · Jan 2013
  • Source
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    ABSTRACT: In this paper an advanced system-level TLP probing technique is presented to evaluate the ESD and EMI performance of a powered system applicable to high speed interfaces. It allows to detect hardware and software fail thresholds to assess the performance of an ESD/EMI protection solution. The method is demonstrated on a Intel mobile phone reference platform.
    Full-text · Conference Paper · Jan 2013
  • Mayank Shrivastava · Harald Gossner
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    ABSTRACT: This paper reviews electrostatic discharge (ESD) investigations on laterally diffused MOS (LDMOS) and drain-extended MOS (DeMOS) devices. The limits of the safe operating area of LDMOS/DeMOS devices and device physics under ESD stress are discussed under various biasing conditions and layout schemes. Specifically, the root cause of early filament formation is highlighted. Differences in filamentary nature among various LDMOS/DeMOS devices are shown. Based on the physical understanding, device optimization guidelines are given. Finally, an outlook on technology scaling is presented.
    No preview · Article · Dec 2012 · IEEE Transactions on Device and Materials Reliability
  • Mayank Shrivastava · Harald Gossner · V. Ramgopal Rao
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    ABSTRACT: A novel drain-extended FinFET device is proposed in this letter for high-voltage and high-speed applications. A 2 × better RON versus VBD tradeoff is shown from technology computer-aided design simulations for the proposed device, when compared with a conventional device option. Moreover, a device design and optimization guideline has been provided for the proposed device.
    No preview · Article · Oct 2012 · IEEE Electron Device Letters

Publication Stats

750 Citations
92.45 Total Impact Points

Institutions

  • 1999-2011
    • Infineon Technologies
      München, Bavaria, Germany
  • 2007
    • Stanford University
      Palo Alto, California, United States
  • 2004
    • Technische Universität München
      • Department of Technical Electronics
      München, Bavaria, Germany
  • 1999-2001
    • Vienna University of Technology
      • Institute of Solid State Electronics
      Vienna, Vienna, Austria