B. Kellerman

MEMC Electronic Materials, Inc., Санкт-Петербу, Missouri, United States

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Publications (7)7.87 Total impact

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    ABSTRACT: In this work we examine the influence of thermal oxidation on the electrical characteristics of ultra-thin strained silicon layers grown on relaxed Si0.78Ge0.22 substrates under moderate to high thermal budget conditions in N2O ambient at 800 °C. The results reveal the presence of a large density of interfacial traps which depends on the oxidation process. As long as the strained silicon layer remains between the growing oxide and the underlying Si0.78Ge0.22 layer, the density of interface traps increases with increasing oxidation time. When the oxidation process consumes the s-Si layer the interface state density undergoes a significant reduction of the order of 40%. This experimental evidence signifies that the strained silicon–Si0.78Ge0.22 interface is a major source of the measured interfacial defects. This situation can be detected only when the front SiO2-strained silicon interface and the rear strained silicon–Si0.78Ge0.22 interface are in close proximity, i.e. within a distance of 5 nm or less. Finally, the influence of the material quality deterioration—as a result of the thermal treatment—to the interfacial properties of the structure is discussed.
    Full-text · Article · Jun 2011 · Thin Solid Films
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    ABSTRACT: In this work ultrathin strained silicon layers grown on relaxed Si <sub>0.9</sub> Ge <sub>0.1</sub> substrates were oxidized under high thermal budget conditions in N <sub>2</sub> O ambient at 800 ° C . The results indicate that the density of interface traps depends on the extent of the oxidation process. If the strained Si layer is totally consumed the density of interface traps reduces to almost half the value as compared to the case where a part of the strained Si layer still remains. The results indicate that the two existing interfaces of the strained Si layer, the SiO <sub>2</sub> /strained-Si and the strained- Si / Si <sub>0.9</sub> Ge <sub>0.1</sub> , contribute in parallel to the measured interface trap density. In addition, the buried strained- Si / Si <sub>0.9</sub> Ge <sub>0.1</sub> interface constitutes a major source of the observed high density of interface traps.
    Full-text · Article · Jul 2009 · Journal of Applied Physics
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    ABSTRACT: In this work the influence of thermal oxidation and subsequent thermal processing on the electrical characteristics of strained-Silicon (s-Si), MOS capacitors was studied. Strained-Si/Si1 − xGex/Si substrates of two different strain levels (10% and 22% Ge content) were oxidized within the temperature range of 800 °C to 900 °C for various time intervals. Capacitance-Voltage measurements reveal that the response of the MOS capacitors depends mainly upon two factors: a) the extend of the s-Si layer oxidation, i.e. the remaining s-Si thickness and b) the duration of the post-oxidation annealing in inert ambient. Both factors influence the interfacial properties of the structures. Additional oxidation experiments in N2O ambient indicate a significant influence of the process conditions on the quality of the oxidized structures.
    Full-text · Article · Nov 2008 · Thin Solid Films
  • T. Dao · M. Seacrist · M. Ries · B. Kellerman
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    ABSTRACT: Consumer wireless products require low power technology to enable extended battery life. Planar Double Gate FDSOI technology had been reported in the Semiconductor industry as having reduced leakage, almost double the drive current, close to ideal subthreshold slope, reduced SCE, and reduced DIBL. However, in the past five years, planar double gate technology has been largely ignored because of the manufacturing challenges. These include the construction of the bottom gate underneath the FET body, the alignment of the bottom gate to the top gate, and the difficult task of incorporating metal gate or high K dielectric material for the bottom gate fomiation. In the past year, there has been significant renewed interest based on the increase in reports published by semiconductor companies, research labs and universities on the planar double gate manufacturing process. Planar Double Gate technology is one of a few technologies being considered as technology to replace planar bulk transistors in 32nm technology and beyond. High K and metal gales are also proposed to be implemented before or at this same technology node. In this paper, for the first time, we report Freescale Semiconductor and MEMC collaboration to provide SOI wafers with bottom gate structures, SiON / Polysilicon and high-K / metal gates, under the single crystalline silicon channel layer.
    No preview · Article · Jan 2007
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    ABSTRACT: In the present work we perform a systematic study of oxidation of very low energy nitrogen-implanted strained-silicon in terms of oxide growth, structural characterization of the implanted strained-silicon substrate and electrical properties of the ultra thin oxides as a function of the substrate strain level. Low energy (3keV) nitrogen (N2+) implantation was performed in strained-Si/SiGe/Si substrates of various strain levels and oxidations were carried out for different times at 850°C. It has been found that nitrogen implantation efficiently blocks silicon oxidation, independently of the strain level of the substrate. TEM analysis revealed the full absence of extended defects in the strained-silicon substrate after the thermal treatments. The grown oxides exhibit very good electrical properties in terms of interface trap densities and leakage currents.
    Full-text · Article · Dec 2006 · Materials Science and Engineering B
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    ABSTRACT: This paper demonstrates for the first time the scalability of source/drain current enhancement on low-doped thin film strained silicon on insulator (sSOI) substrate. Current improvement is maintained in narrow channel NFETs despite the relaxation from biaxial to uniaxial tensile strain after mesa patterning. Using strained contact etch-stop layers (sCESL), additional boost is achieved in short devices, resulting in 50% improvement in the drive current of 50 nm gate length devices with respect to conventional reference SOI process.
    No preview · Conference Paper · Oct 2005
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    ABSTRACT: Reliability studies were conducted on MOS devices using strained Si on relaxed Si 1-xGe x buffer layers with up to 40 % Ge. Time zero and time dependent dielectric breakdown data are presented. Hot carrier reliability results on strained Si / Si 0.85Ge 0.15 are discussed, For lower strain levels, hot carrier reliability of strained Si MOSFETs was found to be better than bulk Si devices, time zero dielectric breakdown voltages were slightly higher and time dependent dielectric breakdown behavior was comparable to bulk Si devices. Significant drive current enhancement was observed for 15 and 20 % substrates. However, at higher levels of strain, surface roughness and relaxation of the strained Si degrade both the reliability and performance in samples with 40 % Ge in the buffer layer.
    No preview · Article · Jan 2005